NVIDIA Accelerators: Hopper → Blackwell → Vera Rubin → Rubin Ultra → Feynman

NVIDIA sells a cadence: an annual rhythm of accelerator generations, each one redrawing the rack, the fabric and the power chain beneath it. The question is not which GPU is fastest. It is which rung of the ramp you commit your building to, and what the next rung costs if you guessed wrong. Since 2022 the unit of purchase has moved up. It went from the H100 as a board, to the HPE GB200 NVL72 profile as a 132 kW rack you buy whole, to the Vera Rubin NVL72 as a 72-GPU rack on AC-fed power shelves. The announced Rubin Ultra generation goes further: the Kyber NVL144 rack on 800 VDC and the eight-rack NVL576 system. Each move can commit the facility to a new interface. A roadmap announcement is neither a delivery promise nor an accepted rack. You can defer the silicon, but you cannot defer the floor loading, the water and the interconnection slot the silicon implies.

This chapter reads the roadmap as a series of decisions and their downstream costs. It covers per-GPU specs across Hopper → Blackwell → Blackwell Ultra → Vera Rubin → Rubin Ultra → Feynman. It treats the NVL system, not the GPU, as the unit of procurement, because the scale-up domain you buy (8 → 72 → 144 → 576 GPUs) has become a strategic commitment rather than a datasheet line. It follows the disaggregated-inference fork that Rubin CPX opened and Groq's LPU/LPX decode racks now answer. And it weighs the annual cadence, which compresses competitors' design windows and can pressure your economic refresh schedule without changing book life. Per-GPU NVLink bandwidth appears here as a datasheet attribute. The NVLink/NVSwitch fabric that aggregates it has its canonical home in Chapter 8.2.

The instinct is to compare generations on peak FLOPS. That is the marketing-number trap (Chapter 7.1): the headline figures are sparse FP4 with the asterisks stripped, and they tell you little about what you must build. What cascades through your facility is rack power. A four-server DGX H100 air-cooled rack comes to about 41 kW at maximum input, before rack networking. The HPE GB200 NVL72 profile is rated 132 kW and requires direct-to-chip liquid. A GB300 NVL72 needs up to 142 kW in NVIDIA's reference architecture and up to 155 kW peak in Lenovo's rating. NVIDIA's DSX reference design plans the Vera Rubin VR200 NVL72 at a 330 kW cabinet facility design basis. Rubin Ultra's Kyber rack (NVL144) targets ~600 kW on an 800 VDC bus. Those are different OEM operating profiles, facility allowances and roadmaps, not a 15× measured power trajectory.

A hall scoped for the previous generation needs an interface-by-interface retrofit check. You cannot upgrade a 40 kW air hall to a 132 kW liquid hall by swapping racks. Check the floor loading against the populated operating mass and point loads of the OEM rack you buy, and confirm that its airflow, electrical headroom and facility water each fit the operating profile you picked. The density wall (Chapter 5.1) and the DLC default (Chapter 5.4) follow from which rung of this ramp you bought into. The power curve governs; the compute curve follows.

Hopper (H100, 2022 / H200, 2024) is the generation most of the installed base still runs. H100 ships 80 GB of HBM3 at ~3.35 TB/s, ~700 W TDP, an FP8 Transformer Engine and NVLink 4 at 900 GB/s per GPU. H200 is the same compute die with 141 GB of HBM3E at ~4.8 TB/s, a memory-bandwidth refresh that helps inference decode disproportionately. Hopper is air-coolable, which is exactly why it became the default and why the jump to Blackwell broke so many facility assumptions.

Blackwell (B200 / GB200, 2024–2025) is a dual-die GPU: two reticle-limited compute dies on one package behave as a single CUDA device over a 10 TB/s die-to-die link. HGX B200 carries 180 GB of usable HBM3E. NVIDIA's current GB200 specification gives 372 GB across the superchip's two GPUs, which is 186 GB usable per Blackwell GPU and ~13.4 TB across an NVL72, against the 192 GB raw figure that earlier material quoted. A second-generation Transformer Engine adds native FP4, and NVLink 5 runs at 1.8 TB/s per GPU. The GB200 superchip pairs two Blackwell GPUs with one Grace CPU over NVLink-C2C. Blackwell Ultra (B300 / GB300, 2025) lifts HBM to 288 GB and adds steady-power and transient-mitigation features (capacitor energy storage, ramp smoothing). They exist because a GB300 NVL72 rack (Lenovo: 135 kW TDP, up to 155 kW peak) swinging between idle and full all-reduce is a grid problem (Chapter 7.12).

Vera Rubin (2026) is the next platform, not just a chip. "VR200" is supply-chain and roadmap shorthand, not NVIDIA's spelled-out name. The Rubin GPU is again dual-die and sits on a CoWoS-L package, though NVIDIA has not said how many reticles the interposer spans. It carries ~336 billion transistors (1.6x Blackwell), 288 GB of HBM4 across 8 stacks at 19.2 TB/s (NVIDIA's shipping specification; the January 2026 announcement said up to ~22 TB/s), fifth-generation Tensor Cores and NVLink 6 at 3.0 TB/s per GPU. The Vera CPU is NVIDIA's custom Arm successor to Grace. The rack-scale unit is the NVL72: 72 Rubin GPUs and 36 Vera CPUs. (NVIDIA briefly marketed it as "NVL144" by counting the 144 compute dies inside the 72 dual-die packages, then reverted to the package-based NVL72 name at CES/GTC 2026.) NVIDIA quotes ~3.6 EF NVFP4 inference (sparse) and ~1.26 EF FP8 training (dense) per rack, with ~216 TB/s of scale-up NVLink bandwidth. Production racks have been shipping since June 2026 (Dell's first racks went to CoreWeave).

Rubin Ultra is where the unit of purchase jumps again, on a contested date: NVIDIA's target is H2 2027, and SemiAnalysis reported 2028 in July 2026. As first announced at GTC 2025, it packs four compute dies per package (~100 PFLOPS FP4, 1 TB of HBM4E per package). It deploys two ways. The ~600 kW Kyber rack (NVL144) holds 144 quad-die packages, or 576 GPU compute dies, on 800 VDC, at ~15 EF FP4 inference and ~5 EF FP8 training. Kyber first ships with Rubin Ultra as a standalone 144-package rack, and NVIDIA presents eight linked Kyber racks (NVL1152) as the scale-up path into Feynman. The NVL576 system links eight MGX NVL72-class racks into one 576-GPU optical NVLink domain, and SemiAnalysis (July 2026) expects it to slip or ship in small volumes. Treat the package specs as in flux. Supply-chain reports from Apr–Jun 2026 said Rubin Ultra was scaled back to a dual-die "2+2" Kyber board layout over CoWoS-L warpage and yield. A SemiAnalysis report of 30 June 2026 gave it two compute dies, not four, and in September 2026 SemiAnalysis put its memory at 192 GB per GPU, not 1 TB. NVIDIA has confirmed neither. The ~600 kW rack power remains an announced planning point.

Feynman (2028) is the next architecture on the roadmap. It is paired with the new Rosa CPU, advanced 3D die stacking and NVLink 8, with the ConnectX and Spectrum generations advancing in lockstep. It is widely expected, though NVIDIA has not confirmed it, to move to a sub-2 nm TSMC node with backside power delivery. The public roadmap targets an approximately annual platform cadence. Dates, product configurations and volume availability remain roadmap commitments until shipped and independently verified.

The rack-power column governs this table, not the compute numbers. Compute grows impressively, but it is the easy part, and its delivery and packaging schedule is itself a material risk. What strands capital is the rightmost columns. The rack unit changes shape (board → 72-GPU rack → 144 → 576), rack power climbs by an order of magnitude, and the cooling and voltage architecture flip underneath. Moving between generations means checking every interface again: rack geometry, mass and floor reactions, power topology and transients, coolant and the TCS and FWS conditions, residual air, fabric, controls, safety and service routes. Reserved capacity can shorten that work. Some moves take a single upgrade; others mean tearing out plant. The generation you choose is the substrate you commit to.

The Rubin line crossed from roadmap to silicon in mid-2026. CoreWeave brought up and validated the industry-first Vera Rubin NVL72 rack on June 1, 2026 (Livingston, NJ; Dell PowerEdge XE9812-integrated): 72 Rubin GPUs plus 36 Vera CPUs, ~3.6 EFLOPS NVFP4 (sparse) and 216 TB/s of NVLink 6 at shipping spec. CoreWeave's announcement quoted NVIDIA's pre-shipment 260 TB/s. On 2026-09-30 CoreWeave announced limited availability, with hundreds of Rubin GPUs across multiple regions and Cognition running production workloads. That is not an unrestricted general-availability announcement. The power basis is now published too. Pegatron's RA4803-72N3 specifies 188 kW (Max Q) / 228 kW (Max P), while NVIDIA DSX sets a 330 kW cabinet TDP facility design basis. Size irreversible infrastructure to the facility design basis, and run energy and TCO models on the chosen operating profile.

Through Hopper, the unit was the 8-GPU HGX board and the scale-up domain was 8 GPUs wide. Blackwell broke that model. The GB200 NVL72 fuses 72 Blackwell GPUs and 36 Grace CPUs into a single NVLink domain: 18 compute trays and 9 NVSwitch trays joined by a copper NVLink spine that carries ~130 TB/s of aggregate rack bandwidth across more than 5,000 in-rack copper cables. The rack delivers ~1.44 EF of FP4 compute (sparse). Every GPU has load/store addressability over NVLink to ~13.4 TB of distributed HBM across the domain. Remote access does not make every GPU's memory local, uniform-latency or universally cache-coherent. The integrated rack is the procurement and acceptance boundary, including when an OEM assembles it from qualified parts. That makes the scale-up domain size a purchasing decision that sets your parallelism ceilings until your next refresh.

The boundary keeps moving up. Supermicro's Vera Rubin shipping announcement (2026-09-23) offers a DCBBS Scalable Unit blueprint: 16 NVL72 compute racks holding 1,152 GPUs and 331 TB of HBM4, plus the power, cooling, storage and networking around them. Its CDUs are rated 1.8 MW each and run N+1, and Supermicro sizes the whole unit to fit within 5 MW. That is Supermicro's blueprint, not a rating that carries over to another OEM. Define the contracted power and cooling duties and the acceptance scope for the complete configuration you buy (Chapter 7.13).

The consequence runs both ways. A wide domain (72, 144 or 576 GPUs) lets you keep tensor-parallel and pipeline-parallel groups, and especially wide expert-parallel MoE inference, entirely inside the NVLink fabric instead of spilling collectives onto the slower back-end network. Inside the fabric, per-direction bandwidth is about an order of magnitude above the scale-out NIC: 18x for GB200 on a 400G port, 9x for GB300 on 800G, and 7.5x for Vera Rubin on 1.6 Tb/s. Wide-EP MoE serving (for example EP32 vs EP8) is the canonical workload that the big domain unlocks (Chapter 8.2). But a wide domain you do not use is stranded capital. A latency-bound 8B-parameter inference service pinned to a 72-GPU NVLink rack pays for a fabric it never lights up. Buy the smallest supported domain that your working set and measured collectives require. The NVL system is a commitment, not a default.

Rubin opens a second, quieter fork that reshapes the inference BOM. Long-context inference has two phases with opposite hardware profiles. The context (prefill) phase reads and encodes the entire input. It is compute-bound, hungry for FLOPS and light on memory bandwidth. The generation (decode) phase emits tokens one at a time. It is memory-bandwidth-bound and latency-sensitive, and it leans on HBM and the KV cache. A monolithic GPU sized for decode (expensive HBM) overpays to do prefill, and a GPU sized for prefill starves on memory during decode. NVIDIA's original answer was Rubin CPX, announced 2025-09-09: a context-phase accelerator with ~30 PFLOPS NVFP4, 3x attention acceleration over GB300 and 128 GB of GDDR7 rather than HBM, a memory NVIDIA described as cost-efficient for this compute-bound role.

NVIDIA then shelved CPX. At GTC 2026 NVIDIA's Ian Buck told reporters CPX had been pulled so the company could put LPU decode first, leaving room to revisit it in a later generation (press Q&A transcript, Tom's Hardware, 2026-03-23). The Next Platform and The Elec reported the same. As of 2026-10-16 NVIDIA had not announced a permanent cancellation or a revised delivery date, so treat CPX as announced and not shipping. Analyst Ming-Chi Kuo, though, wrote at the end of August 2026 that NVIDIA had brought CPX back for Q1 2027 production, swapping GDDR7 for 168 GB of HBM4 and moving it into a separate rack of 64 to 256 GPUs (TechNews, 2026-09-02). NVIDIA has not confirmed it. If it holds, a dedicated prefill tier returns without the cheap-memory case it was announced on, so do not plan a prefill tier around it until NVIDIA publishes the part. For now, the Rubin GPUs keep prefill and attention, and Groq LPU silicon takes the latency-critical decode FFN/MoE layers. NVIDIA licensed that technology, non-exclusively, in December 2025 (about $20B, as reported).

Two Groq products are easy to conflate. The chip is the Groq 3 LPU, an SRAM-based inference processor with ~500 MB of on-chip SRAM, ~150 TB/s of SRAM bandwidth and no HBM. The rack is the LPX: 256 LPUs with ~128 GB of aggregate on-chip SRAM, the deployable unit. NVIDIA took a non-exclusive licence to Groq's inference technology and sells LPX as a decode tier inside the Vera Rubin platform. NVIDIA announced full production for Groq 3 LPX on 2026-08-24, and Nebius is the first AI cloud to adopt it. The LPU does not run CUDA natively. It uses a compiler-scheduled execution backend that NVIDIA coordinates with the GPUs through Dynamo, so an LPX tier adds a second backend to test and support inside an otherwise all-NVIDIA fleet. Performance figures for LPX are NVIDIA's (vendor claims).

A footnote on commercial structure, not a silicon change. Groq itself stays independent after the December 2025 licence. On 2026-08-12 Groq announced it had become an NVIDIA Cloud Partner and planned to equip existing data centers with NVIDIA accelerated computing. That cloud business is separate from NVIDIA's licensed LPX product.

The decision for long-context (million-token) workloads is whether to disaggregate serving or stay monolithic. In the arrangement NVIDIA describes for Rubin and LPX, the Rubin GPUs handle prefill and decode attention and keep the KV cache, while Groq LPX decode racks run the decode FFN/MoE layers. The two pools exchange intermediate activations at each relevant layer for every token. Classic prefill–decode disaggregation, which NVIDIA also describes for LPX, works differently: Rubin hands the KV cache to LPX once per turn, and LPX runs the whole decode. NVIDIA projects that the split lowers cost per token and interactive latency at long context, because token-by-token decode runs on Groq's deterministic SRAM silicon instead of tying up HBM GPUs. Confirm that on your workload by comparing both options at matched quality, latency and throughput, on complete-system power and cost. The split costs you a more complex serving stack, with separate pools and attention-to-FFN ratio tuning, and a fabric that carries activation exchange at per-token latency (Chapter 10.11). Nor does the fork stop at long context. Besides the two splits just covered, NVIDIA describes a third arrangement built around an external drafter. Each of the three puts a different traffic volume and latency requirement on the fabric. Name the arrangement before you derive a fabric requirement from it.

The cadence is a competitive instrument as much as a delivery schedule, and it cuts two ways. Against competitors, a yearly architecture shrinks the window any challenger has to close a gap. If AMD or a custom-ASIC roadmap matches Blackwell just as a qualified Rubin system arrives, the comparison resets (Chapter 7.3, Chapter 7.5). The software moat (CUDA and the NCCL/Dynamo/TensorRT stack) compounds this: a one-year hardware tick gives the ecosystem a fresh target every twelve months. Against the buyer, the same cadence accelerates depreciation. Bears such as Michael Burry put a frontier accelerator's economic life at 2–3 years, because next year's part does the same work at materially lower cost per token. That view is contested: Goldman Sachs reports that AI accelerators are typically given a 4–6-year useful life, and operators book 5–6 years. The cadence that protects NVIDIA's lead also shortens your amortization runway.

That sets up the buyer's real decision: ride every generation, or skip? Riding each step can improve output per dollar, but it means continuous capital outlay and new power, cooling and fabric limits every year. Skipping a generation (for example Hopper → Rubin, bypassing Blackwell) reduces churn and lets one substrate investment serve longer, at the cost of running a generation behind on token economics during the gap. Two variables decide it. One is your residual-value assumption: do used GPUs hold enough value to backstop the refresh (Chapter 1.8)? The other is whether your facility can even accept the generation you would skip to. A 40 kW air-cooled position cannot take a roadmap 600 kW Kyber profile without facility work. An announcement gives you a refresh option. Exercise it only when the cost model in Chapter 1.8 (hardware, migration, facility work, downtime and the value of keeping the fleet) says it pays.

A defensible accelerator strategy applies the same discipline that governs facility scoping (Chapter 1.1): sort decisions by the cost of changing your mind. The roadmap makes some things reversible and some irreversible, and they are not the ones people assume.

• Reversible (defer, re-decide at refresh): the specific accelerator generation within the hall's power and cooling limits (a hall plumbed for ~140 kW liquid still needs the exact GB200 or GB300 electrical, liquid, room-air and service profile checked); the HGX-vs-NVL choice for an inference fleet; the disaggregation decision for inference serving; and the ride-vs-skip refresh cadence.
• Irreversible (commit at scoping): whether the hall is plumbed for liquid at all; the floor-loading basis, which is ~3,000–3,300 lb for a GB200/GB300 NVL72 wet rack, ~4,000 lb for Vera Rubin NVL72, and the OCP Open Data Center targets of 8,000 lb per rack (15,000 lb with an AC/DC sidecar) if the hall must take 2027–2028 hardware (targets, not shipping-rack measurements; Chapter 6.1); the electrical capacity and voltage path (415/480 VAC vs an 800 VDC future); reserved physical headroom (busbar runs, pipe racks, switchgear room) for the next density step; and Rubin readiness, because VR200 NVL72 at a 330 kW cabinet facility design basis is a substrate step rather than a rack swap. Price the option premium against later retrofit cost: a reservation is not automatically cheap, but it usually costs less at scoping than after energization.

The strategic move is the same as everywhere in this guide: convert irreversible decisions into reversible ones while the option is cheap. Reserve the busbar capacity and water for a density step-up you have not committed to. Buy into the NVL domain your workload uses today, but provision the substrate for the domain you might buy in two years. Design the rungs you can reach into the building before you need them. Chapter 7.13 records manufacturer, revision, mode, interfaces and enabling works, and Chapter 1.8 prices the refresh.