Power Topology Foundations & Voltage Selection

Power reaches a GPU only after a relay of voltage transformations, and each link in that relay costs something. High-voltage transmission arrives at the fence. An on-site substation steps it down to medium voltage, transformers drop it to low voltage, a UPS conditions it, and a PDU or busway distributes it. A power shelf then rectifies it to a DC bus, and an on-board VRM bucks that bus down to the sub-volt rail the silicon runs on. Every voltage-conversion stage has an efficiency that depends on the architecture. PDU and busway distribution do not convert voltage, but they still take copper, floor area, cooling and capital. Where you set the voltages and how many times you convert is the design question. In a power-bound era the answer comes from comparing complete chains: deleting a stage helps only if the stages that remain, plus the route losses, come out ahead.

Two forks dominate the design basis. The first is the region you build in. Grid frequency and the locally adopted standards (IEC, ANSI/IEEE or others) affect equipment ratings and protection. Frequency and standards family are separate attributes, and the regional basis also re-prices your switchgear lead times. The second is AC to the rack versus DC-disaggregated, which decides how many conversion stages survive into 2027. Around those two forks the chapter builds the voltage taxonomy that names every rail (HV/MV/LV on the AC side; 12 V, 48-54 V, ±400 V and 800 V on the DC side). It then covers designing for the real peak (EDPp, not TDP), the per-rack density tiers that set the substrate, and the lead-time reality that reshapes topology before any engineering matters.

Before the forks, fix the map. A hyperscale AI campus moves power through a sequence of functions, and how those functions are packaged changes with the topology. You need to know which stage a topology decision touches. The canonical chain, utility to chip:

• HV transmission → on-site substation. Power arrives at 115–500 kV (132–400 kV in IEC regions), and a customer- or utility-owned substation steps it to medium voltage. This is the scarcest, longest-lead and least reversible link: the interconnection queue and the substation set the schedule. → Chapter 4.2.
• MV distribution. The 11/13.8/33/34.5 kV class carries power across the campus to pad-mounted or block transformers. Radial, primary-selective or ring layouts set the campus single-line and the fault-current picture. → Chapter 4.2.
• LV / transformer. The block or unit transformer drops MV to the distribution LV class, 400 V (IEC) or 480 V (ANSI) three-phase, which feeds the white space. AI's switch-mode load makes the harmonic spectrum and the synchronized load profile transformer inputs, not just the voltage ratio; active-PFC equipment can draw low-distortion current. → Chapter 4.4.
• UPS. Double-conversion or eco-mode conditioning and ride-through sit between the transformer and the load in AC architectures. In DC architectures that role is moving toward rack BBUs and facility BESS. → Chapter 4.5.
• PDU / busway → rack. Overhead busway or cable-and-PDU carries LV to the rack, where a rack PDU (commonly 415 V three-phase, A/B dual-fed) lands it on the racks. → Chapter 4.6.
• DC bus → VRM → chip. A power shelf rectifies AC to the in-rack DC bus (48/54 V today, ±400/800 V in the DC-disaggregated future). Rack and board DC/DC conversion produces intermediate rails, and the final VRM/VRD bucks its input to the <1 V GPU core rail at hundreds of amps. This last conversion is the most demanding, thermally and electrically. → Chapter 7.12.

Part 4 is organized around these links. This chapter makes the decision above all of them: how many of these stages exist at all, and at what voltage.

Voltage is classified by class on the AC side and by rail on the DC side, and the two meet at the rectifier. On the AC side, class boundaries depend on the governing IEC document and the application. IEC low voltage extends through 1 kV AC, for example, while your project and utility define MV and HV, so do not assume one universal 35 kV boundary. The 400/480 V feed to the hall is low voltage. The DC side is where the 2026 action is. The legacy in-rack bus is 12 V (enterprise servers) or 48–54 V (OCP / GPU racks, the de-facto standard since the Open Rack V3 era). The disaggregated future is an 800 V rail-to-rail class, built as bipolar ±400 V about a midpoint (OCP Mt. Diablo 1.0.0, effective October 8, 2026, calls it differential 800 VDC) or as a unipolar nominal 800 V bus in NVIDIA's 800 VDC architecture.

Voltage matters because of the conductor. Power is voltage times current, and resistive loss is current squared times resistance. For a fixed power, raising the voltage cuts the current linearly and the I²R loss quadratically, so an 800 VDC path carries the same power with less copper. Chapter 4.7 checks the power-per-gauge headline NVIDIA publishes against a first-principles comparison and explains why a figure without a stated basis should not drive cable sizing. NVIDIA also reports an end-to-end efficiency gain of up to about 5 points for its own design (NVIDIA, 800 VDC Architecture, 2025–2026). At a fixed gigawatt of input, 5 efficiency points is 50 MW more useful output. At fixed chip output, divide by each chain's efficiency before claiming avoided generation, cooling or cost.

Conversion-stage accounting makes this concrete. Count every place the voltage changes and every place AC becomes DC or the reverse, and give each stage an efficiency and a cost. The legacy AC chain runs MV transformer → LV → UPS double-conversion (AC→DC→AC) → rack PSU (AC→DC) → VRM (DC→DC). That is four functional conversion packages, counting the UPS's internal AC→DC→AC stages as one, and it delivers about 80–87% utility-to-VRM, about 82% on a representative path. Count any LV distribution or busway loss as a separate multiplier. A direct MV-to-DC chain has three packages: the MV/DC converter, the rack DC/DC and the final converter. The SemiAnalysis May 26, 2026 SST/800 VDC model reports ~87%, and the guide's three-package case below also rounds to 87% from assumed stage efficiencies. Neither proves a five-point plant improvement unless both chains are compared at the same load. What moves the headline is the product of the retained efficiencies. Deleting a package can help, but a lossy high-ratio converter or extra route loss can erase the gain.

This guide is global, and the local design basis reshapes power topology before any engineering judgment enters. Specify six fields independently: grid frequency, nominal voltages, adopted installation code, equipment and product standards, earthing, and utility grid code. One project basis may pair 50 Hz with 400 V three-phase / 230 V single-phase, IEC 60364 installation rules, IEC 61439 assemblies, a TN-S, TT or IT earthing arrangement, and IEC 61850 utility automation where applicable. Another may pair 60 Hz with 480 V three-phase / 277 V single-phase, NEC (NFPA 70), and ANSI/IEEE equipment standards. Build the equipment schedule from the project basis you adopt. A two-region label tells you neither the IEC lineage nor the frequency.

The consequences cascade. The frequency sets transformer flux and therefore core size. At unchanged flux density and volts per turn, 50 Hz needs more core area than 60 Hz, but the vendor's quoted mass and dimensions still set pad loading, transport and crane selection. The LV voltage (400 vs 480 V) re-ratios every step-down transformer and re-sizes every feeder. Power is fixed, so 480 V carries the same kW at ~17% less current than 400 V, and an identical hall distributed at 480 V runs less current through its LV runs. The earthing regime sets touch voltage, fault detection and how the whole protection scheme behaves, depending on whether you bond the neutral solidly (TN-S), through impedance, or leave it isolated (IT). Chapter 4.11 engineers it in depth, but you select it in the project design basis rather than inferring it from region. The code regime decides which switchgear, breakers and arc-flash methodology you can procure. An IEC-spec GIS lineup and an ANSI-spec metal-clad lineup are different supply chains with different lead times.

You inherit the grid and the adopted code, then select compatible voltages, standards, earthing and equipment. Price that choice at scoping time. A design developed against the wrong basis, such as a US template dropped onto a Frankfurt site or the reverse, fails diligence and gets re-engineered late, when re-engineering costs the most.

Inside whichever regional basis you inherit sits the live 2026 decision: how the last several stages of the chain are arranged. There are two coherent answers. They differ in the number of conversions, the location of the rectifier and the maturity of the ecosystem.

The legacy AC-to-the-rack path keeps AC all the way to the cabinet. MV transforms to 400/480 V LV, a facility UPS conditions it, busway or PDU carries AC to the rack, and an in-rack power shelf rectifies it to the 48/54 V DC busbar that feeds the boards. This is the established path, with a broad supplier base, familiar installation practice and settled code treatment. What you actually get still depends on the ratings, configuration and delivery dates of the specific offer. The path carries the most conversion stages and rectifies once per rack, which multiplies PSU count, fan count and maintenance surface across thousands of cabinets.

The DC-disaggregated path moves the rectification upstream and out of the rack. In the OCP Mt. Diablo / ±400 VDC pattern (developed by Meta, Microsoft and Google), a centralized sidecar power unit converts to ±400 VDC and feeds disaggregated DC to the IT racks, drawing on the EV industry's 400 V supply chain. The final Mt. Diablo 1.0.0 specification, effective October 8, 2026, scopes one power rack at 800 kW to over 1 MW. In the NVIDIA 800 VDC / Kyber pattern, a solid-state transformer (or staged rectifier) converts MV grid power directly to 800 VDC at the facility level, and the rack carries a single high-ratio DC-DC stage to the board rail. Both patterns move the AC rectifier out of the rack, but the three-package count describes only the direct MV-to-DC version, since a sidecar fed with AC may retain the upstream transformer and UPS. NVIDIA's May 20, 2025 roadmap targeted 1 MW IT racks and beyond starting in 2027. That is a forecast, not a topology rule, so check the interface your supplier actually offers. The cost of the disaggregated path is ecosystem immaturity at the 800 V class. DC breakers and busways rated for it, >1 kV-DC UL listings and SST production are all still ramping in 2026, so you trade a thinner vendor bench and code-pioneering risk for efficiency and density headroom. Chapter 4.7 covers the full engineering of this transition, including the solid-state transformer and sidecar power, with SST harmonics context in Chapter 4.4.

Onsite generation can also feed DC directly. Bloom Energy's September 2026 report proposes fuel cells that supply native 800 VDC, so there is no source-side AC rectifier to count. Judge that option on the DC it delivers toward the chip, and carry fuel-to-electric efficiency, auxiliaries, redundancy, maintenance and transient storage as separate line items. It starts from fuel rather than an MV feed, so don't compare it directly with the ~87% MV-to-final-converter figure. Chapter 3.5 covers the prime-mover choice and Chapter 4.8 covers generation and microgrid integration.

The 400 V end of this path is older than the AI wave. In 2006, Lawrence Berkeley National Laboratory ran a 380 VDC distribution demonstration with 21 participating organizations at Sun Microsystems in Newark, California. It measured about 5–7% less input energy than best-in-class AC and about 28% less than a typical AC chain. The 2008 report warns that the gain depends heavily on which AC reference you pick. Interface standards followed in 2012: ETSI EN 300 132-3-1 and ITU-T L.1200 define a 260–400 VDC input for telecom and ICT equipment, and the EMerge Alliance approved its 380 VDC Data/Telecom Center Standard in early 2013. Production plants followed as well. ABB built an almost-1 MW, 400 V system for green.ch's Zurich-West data center in 2012, with a grounded center tap at ±200 V (ABB Review 4/2013). NTT Communications had eight 500 kW, 380 V systems in service by 2015, ahead of group-wide introduction from FY2016 (NTT Technical Review), and Chinese carriers standardized their own 240 V HVDC class (YD/T 2378-2011). Operators still build this pattern. A DC UPS and battery string float on the bus, routers and servers take DC-input power supplies, and some plants feed on-site solar straight onto the bus through an MPPT controller with no inverter in between. DC UPSs, DC-input PSUs, insulation monitoring and midpoint-grounded buses therefore have more than a decade of field practice at 380–400 V. The megawatt rack, the 800 V class and the SST are what is new.

A common sizing error is to design an AI power chain to the chip vendor's TDP instead of to EDPp. TDP is thermal design power, an input for sizing heat sinks. EDPp is electrical design power at peak, as the supplier defines it for a given point in the chain and a given duration. The two can diverge sharply in AI halls. Synchronous training can produce correlated swings, with thousands of GPUs dropping toward idle during communication phases and ramping together when compute resumes. How large the swings are, and how long they last, depends on the workload, the platform, power caps and rack storage.

Summed chip TDP does not tell you the load at the rack inlet, feeder, UPS or transformer. A component with too little capacity or too slow a response can sag or trip on protection exactly when the cluster is most expensive to interrupt. So size each component for continuous load, peak versus duration, and recovery, and engineer the transient explicitly. That is why modern racks put transient storage at several layers. The power-shelf PSUs in NVIDIA's GB300 NVL72 integrate ~65 J/GPU of electrolytic storage, and in a July 2025 test on a GB200 rack running Megatron with those PSUs, grid-side peak fell by 30%. Rack BBUs remain separate, and facility BESS is increasingly a power-quality device, not just a runtime device.

Chapter 4.5 owns the transient itself (its origin on the die, its propagation and the chip→BBU→BESS mitigation spine), with the on-die origin in Chapter 7.12. It also shows how much oversubscription headroom real fleets leave unused, and how smoothing changes it. This chapter's concern sits upstream. The ratings on the single-line, the breakers and the transformers come from the continuous, peak-versus-duration and recovery limits at each level of the chain. EDPp is one input to those limits, translated through the actual conversion stages and storage controls. A mistake there carries through every stage you designed.

Voltage architecture follows from one number you must commit to early: the per-rack density tier the facility is built to absorb. The 2026 roadmap is steep and well published, which is why the AC/DC fork is urgent rather than academic. A hall whose substrate (substation capacity, MV ring ampacity, conductor pathways, floor loading) is scoped to one generation strands the next.

• ~40 kW/rack: H100-era air-cooled racks (2023). Legacy AC-to-the-rack at 415 V is entirely adequate, and this is the world most existing halls were built for.
• 132 kW nominal: HPE GB200 NVL72.
• 135 kW TDP / up to 155 kW peak: GB300 NVL72 (Lenovo). NVIDIA's enterprise reference architecture separately plans for up to 142 kW for a full rack. Liquid cooling is required, and the rack bus is low-voltage DC at the voltage your OEM's configuration sets.
• 188 kW Max Q / 228 kW Max P: VR200 NVL72 operating profiles (Pegatron, 2026). NVIDIA's DSX reference design plans the Vera Rubin NVL72 cabinet at 330 kW TDP, the basis for power and cooling. If you follow that reference design, size irreversible infrastructure to its 330 kW basis. Base energy models on the operating profile you expect from the system you buy; 188/228 kW belongs to Pegatron's VR200 NVL72 configuration alone. AC feed is still on offer through Vera Rubin NVL72. Flex's power shelf accepts 346–480 VAC three-phase and delivers up to 110 kW at 52 VDC, and NVIDIA's August 2026 whitepaper lists both AC and DC input options for Vera Rubin's 330 kW rack-power architecture. As rack power climbs, the current on the low-voltage DC bus is what pushes the roadmap toward higher voltage. Test the rack bus and the AC route you are offered for current, heat, failure behavior and serviceability.
• ~600 kW facility planning point: Rubin Ultra / Kyber and later. NVIDIA targets H2 2027, while SemiAnalysis reported 2028 in July 2026. NVIDIA's Kyber roadmap pairs this tier with 800 VDC because extending 54 V distribution would take prohibitive rack volume and copper. For scale, OCP's MGX 1.2 rack specification (effective October 6, 2026) allows racks up to 250 kW on a 48 VDC liquid-cooled busbar rated at 5,000 A, less than half this tier. Reserve irreversible pathways for that DC architecture, and keep the rack-level fit-out specific to the generation.

The design discipline mirrors the reversible/irreversible split from Part 1. Pour the substation, MV ring, pathway and floor-loading basis for the high-density DC endpoint, which is costly and disruptive to retrofit. Fit out the rack-level voltage architecture, which you can swap at refresh, to the generation you are buying. Build the chain for 40 kW and you have built for H100-class racks: they can still train, but the building cannot host current rack-scale systems without costly rework. Reserve headroom for the ramp and you keep the ramp open.

One more force reshapes topology before any of the engineering above is settled: what you can actually buy, and when. Power-chain equipment carries some of the longest lead times in the build, and in a power-bound market the lead time is a design constraint. In Wood Mackenzie's Q2 2025 US survey (published October 2025), power transformers averaged 128 weeks and generator step-up units (GSUs) 143 weeks. Its assessment reported in May 2026 put US substation transformers above 160 weeks, and SemiAnalysis reported US GSUs quoted at 3–4 years on June 25, 2026. The US Department of Energy's July 2024 report cites maximum lead times of up to 60 months for US large power transformers rated at 100 MVA or more. Plan on the supplier's delivery commitment, not an average. That date is often the long pole that sets energization. MV switchgear, large UPS modules and SST/DC gear all carry multi-quarter-to-multi-year queues, and the newer DC-disaggregated equipment is the thinnest-supplied.

Procurement therefore reshapes topology in two directions. First, it pulls toward fewer, more available stages, because a topology that needs three exotic transformers you cannot get for four years is just a delay. Second, it can pull toward the DC path or away from it depending on the calendar. The AC-to-the-rack ecosystem is established today, though its long-lead gear is still queued, while the SST/800 VDC ecosystem is ramping. A 2026 ground-break may therefore be forced onto AC distribution for the IT layer even as it builds the substrate for DC. Every long-lead power item belongs in the lead-time register maintained in Chapter 2.3, and the voltage architecture you commit to should be cross-checked against that register before it is frozen. A single-line is only as good as the delivery dates of its long-lead gear, and equipment that energizes after the accelerators it serves are ready to draw load is a design failure, however elegant the drawing.