The Rack as Integration Unit

For thirty years the rack was the least interesting object in the data center: a 19-inch steel cabinet, 42 rack-units tall, bolted to the floor, with servers slid into it. It had no opinion about power, cooling or networking. Those arrived from elsewhere, and the rack merely held the boxes that used them. AI ended that. A GB200 NVL72 is best read not as 72 GPUs in a rack but as a rack that happens to contain 72 GPUs: factory-integrated compute trays, power shelves, DC busbar, liquid manifolds, NVLink spine, top-of-rack switches and service cabling, built and validated as one system.

For a rack-scale scale-up platform, the smallest thing you can meaningfully buy, ship, power, cool, cable and accept is the whole frame: the integration unit. Air-cooled PCIe and HGX-class servers still sell by the box, and a workload that does not need a 72-GPU coherent domain should still be bought that way (Chapter 7.8).

This chapter is the canonical home for the rack as an object: its anatomy, its form factors, and how every other physical subsystem now lands on it. It points outward on purpose. Part 4 engineers the power chain inside the rack, Part 5 the liquid loop, Chapter 6.7 the civil mass and anchoring, Part 8 the fabrics and Part 14 the operational telemetry. What stays here is the integration discipline: which rack standard to build a facility around, and the fact that every interior subsystem (busbar pitch, manifold geometry, cable management, BBU shelf, DCIM model) is dimensioned to that frame and inherits its constraints for a decade. The frame outlives three GPU generations.

The integration unit is the level at which a thing is designed, procured, tested and warranted as one. For decades that level was the server: you bought a 2U box, the vendor warranted it, and the rack was just where it lived. The scale-up domain pushed the unit up a level. When 72 GPUs must behave as one coherent accelerator over a copper NVLink spine that tolerates only sub-metre reach, the 72 GPUs, the nine NVSwitch trays, the spine, the busbar and the manifold cannot be assembled by independent vendors and hoped to fit. They must be co-designed to one mechanical, electrical and thermal specification, and that specification is the rack. So the rack is now the smallest independently meaningful object: you cannot buy a third of an NVL72, and you cannot service one GPU without respecting the loop and the spine that bind the whole.

The rack is also where the four facility spines, power, cooling, network and data, converge, terminate and have to coexist in the rear plane of a frame roughly 600 mm wide externally and more than 1,200 mm deep. Each spine has a canonical chapter of its own, and none can be designed without knowing the geometry of the frame it lands in. The civil scope, meaning how a rack of roughly 1.4–3.2 t (by platform) spreads load into the slab and resists seismic events, is its own discipline and lives in Chapter 6.7. This chapter owns everything from the frame inward to the point where each spine becomes canonical elsewhere.

Three frame lineages dominate in 2026, and the differences are not cosmetic: they propagate into every spine. The legacy line is 19" EIA-310, the universal enterprise rack: ~600 mm external width, a nominal 19-inch equipment mounting width, and 1.75" rack-units (U). The frame drawing, not the nominal width, gives the clear aperture and external dimensions. It is the default for air-cooled and modest-density inference, and most existing colocation halls are striped for it. The OCP line is 21" Open Rack V3. Its IT-usable aperture is wider (~537 mm), and it is measured in OpenU (OU, 48 mm, taller than a U). A 48 V DC blade busbar runs the full height of the rear; power and BBU shelves occupy OU positions in the rack, and the side pockets carry cabling. ORV3 was designed for hyperscale serviceability, and it is the baseline that the ±400 VDC OCP Mt. Diablo and 800 VDC sidecar designs extend. The newest line is Open Rack Wide (ORW), Meta's contribution, published as the ORW v1.0.0 specification in April 2026: a wider system standard with its own dimensions and assembly documents, built to give rack-scale accelerators like AMD's 72-GPU Helios the lateral room for trays, manifolds and a scale-up fabric that a single-wide frame cannot hold.

The second axis is depth, and it has grown faster than width. Enterprise racks lived comfortably at ~1,070–1,200 mm. AI racks have pushed past ~1,200 mm and are heading deeper, because the rear of the rack is now contested: liquid manifolds, the OEM's quick-disconnects, blind-mate power connectors and dense cabling all compete for the same plane. NVIDIA's NVL72 MGX rack and its 44RU/48RU manifold variants exist to package that rear congestion. Depth growth is not free. It consumes white-space floor area per rack, lengthens cable and hose runs, and complicates rear-aisle service clearance.

The third axis is weight. It is a civil problem (Chapter 6.7) but it originates in the frame: a populated MGX GB200 and its transport package have different mass and point-load records, and your OEM must supply both. That is why the frame, the slab and the anchoring have to be co-specified.

The newest change is inside the tray. Vera Rubin NVL72, built on NVIDIA's third-generation MGX NVL72 rack, has been shipping since June 2026. Its compute and switch trays are fanless and liquid-cooled, and in the compute tray a printed-circuit-board midplane replaces the internal cables, which is why NVIDIA calls the trays cable-free. The copper NVLink spine between compute and switch trays stays, and the PSUs in the four 110 kW power shelves stay on air. For the integrator, that means far fewer in-tray terminations to inspect at factory integration (L11) and faster tray assembly; what it does to spares and repair is in Chapter 14.6. The Vera Rubin rack and compute-tray designs went to OCP in October 2026, as NVIDIA's contribution to the MGX 1.2 specification.

The rightmost column is the price of getting the frame wrong. A hall striped for 19-inch equipment needs an ORW swept-volume and route check before you know whether containment or aisles must change. An ORV3 power shelf does not make an arbitrary 19-inch rack compatible. An MGX rack's rear plane is so full of manifold and NVLink spine that a cooling or cabling retrofit needs a measured service-clearance and routing check. The frame is the first irreversible interior decision, and the three lineages do not interoperate at the subsystem level even where their external footprint looks similar.

The power spine is where the frame standard bites first. In a legacy 19" rack, power comes in on AC whips to in-rack PDUs, and cords from the PDUs run to each server's own PSUs. Past a few tens of kW per rack, that gets crowded. The OCP world does AC-to-DC conversion in rack power shelves instead, and a vertical blade busbar the full height of the rear replaces the per-server cords. The shelves are still fed by AC whips. NVIDIA's DGX Vera Rubin NVL72 user guide (October 2026) shows each of a rack's four 110 kW shelves on two 100 A whips at 415–480 VAC.

ORV3 operates at 47.5–50.5 V. A first-generation ORV3 HPR shelf delivers up to 33 kW at 50 V nominal (27.5 kW with N+1 modules), and a GB200-class rack stacks six to eight of them. OCP's HPR V2 shelf specification (Meta, 1.0.0, June 2026) puts six 12 kW supplies in 1 OU for 60 kW at N+1, so the same rack load needs about half as many shelves. Vera Rubin NVL72 moves to four 3RU 110 kW shelves. Blind-mate connectors let a tray drop into the busbar without a single bolted cable, a serviceability win that exists only because the busbar geometry is part of the frame standard. The GB200-generation NVL72 MGX busbar is rated ~1,400 A: NVIDIA's OCP contribution keeps the ORV3 width and deepens the profile to roughly double the ampacity.

OCP's MGX 1.2 specification (revision 1.2.0, effective October 6, 2026) calls for a 48 VDC liquid-cooled busbar rated to 5,000 A and allows racks up to 250 kW. Both figures are specification ceilings, not a measured rack. The bar keeps the ORV3 width, grows deeper and takes its own PG25 supply through an MQD-04 coupler, so the rack manifold now feeds the busbar as well as the trays. MGX 1.2 carries NVIDIA's Vera Rubin rack design, yet NVIDIA's DSX reference design plans Vera Rubin NVL72 cabinets at 330 kW TDP, above the 250 kW ceiling. The 330 kW is the facility basis for sizing power and cooling, while OEM datasheets rate the rack's operating profiles at 188 kW Max Q and 228 kW Max P, inside 250 kW.

Do not derive rack power by adding supply and return. A conductor pair carries one circuit current, so 1,400 A at 48 V is ~67 kW delivered, and a ~132 kW continuous rack needs on the order of 2,750 A of aggregate circuit current, from parallel feeds or distributed injection. Take that topology and the per-segment ratings from the OEM power-distribution drawing, not by back-solving the rack's nameplate wattage. The whole power chain (busbar ampacity, shelf ratings, PSU efficiency, the AC-to-DC topology) is engineered in Chapter 4.6 (LV distribution, busway, PDUs) and Chapter 4.7 (the ±400/800 VDC and disaggregated-sidecar revolution). What lives here is the geometry: the busbar occupies a fixed plane of the rear, and it competes with the manifold and the cabling for that plane.

The density ramp forces the frame to anticipate a power architecture it does not yet run. At 54 V, a 1 MW rack draws ~18,500 A, and NVIDIA estimates it would need up to ~200 kg of copper busbar per rack, which does not scale across a campus. That is why the industry is moving to ±400/800 VDC, which carries the same power with less copper (Chapter 4.7). A frame cut today for a 48 V blade busbar may have to host an 800 VDC busbar fed from a sidecar power rack in two generations. The transition has a planned on-ramp: NVIDIA says its MGX-compatible 800 VDC power rack arrives in H2 2026 (NVIDIA, Aug 2026), while the shipping Vera Rubin NVL72 still takes AC-fed in-rack power shelves. Kyber is designed around 800 VDC.

The BBU shelf is rack-level battery ride-through that triggers in milliseconds to absorb the synchronized GPU load step. It occupies OU slots in the rack and is canonical in Chapter 4.5. Liquid cooling does not remove the rack's air path. On Vera Rubin NVL72 the compute and switch trays and the busbar are liquid-cooled, but each of the four 3RU 110 kW power shelves carries six air-cooled 18.3 kW PSUs. The frame still needs front-to-rear air for those shelves. Reserve the shelf volume, and take the residual air duty from the OEM profile (Chapter 5.1). The integration question the rack owns: does the frame reserve the volume and the busbar plane for the next voltage class, or does it lock you to 48 V?

The cooling spine is the most congested object in the rear of the rack and the one most coupled to the frame. A direct-to-chip liquid-cooled rack carries a vertical manifold pair (supply and return) feeding cold plates on every GPU and switch. A GB300 NVL72 has 27 liquid-cooled trays (18 compute, 9 switch) fed by quick-disconnects (QDs) from the rear supply and return manifolds, so there are at least 54 tray-level connections (a supply and a return per tray) before counting any inside the trays (Lenovo GB300 NVL72 product guide). Each one is a potential leak point, and each is a place where a tray must blind-mate into the loop without an operator coupling a hose by hand. Ask the rack maker for the connection schedule that matches your exact rack revision.

A guide heat balance for the HPE GB200 NVL72 gives ~140–220 L/min from its 115 kW liquid load at OCP's 7.5–12 °C rise; PG25 at OCP's 1.25–2.0 L/min per kW gives ~144–230 L/min. The separate QCT GB200 NVL72 reference permits up to 45 °C liquid inlet and 65 °C liquid return. These are independent maxima, not the flow-sizing delta-T. ASHRAE W45 describes the facility-water (FWS) supply capability, not a technology-cooling-loop (TCS) operating pair. Colder supported supply buys thermal headroom at the cost of chiller capex. The dripless, blind-mate couplings that make this serviceable are OCP-standardized, but the frame specification picks the family and size. MGX 1.2 trays blind-mate on UQD-08/UQDB-08 (UQD 2.0.0) where rev. 1.1 used UQD-04, and its fanless I/O bays and busbar use NVIDIA's MQD couplers (OCP MQD/MQDB 1.0.0). The manifold and QD geometry must conform to the frame standard: a manifold designed for an MGX rear plane will not fit an ORW one. The direct-to-chip design (cold plates, coolant chemistry, the technology-cooling vs facility-water loop split) is canonical in Chapter 5.4, and CDU sizing, flow and the coolant-rise rule in Chapter 5.6; the density wall that makes liquid mandatory is Chapter 5.1.

The integration decisions the rack owns are mechanical and operational. Leak detection (rope sensors at the manifold, drip trays, per-tray flow monitoring) is a rack-level instrumentation layer, and its telemetry feeds the DCIM model. The emerging negative-pressure (sub-atmospheric) design is a rack-architecture choice with a real consequence: with the loop below ambient pressure, a small breach pulls air in rather than pushing coolant out. The leak behavior is bought with more complex pumping and tighter CDU control, and the decision is made at the rack/CDU boundary before the loop is plumbed. With dozens of coupling points per rack (at least 54 tray-level connections on a GB300 NVL72) and thousands of racks, expected leak events scale with the joint count. Negative pressure is the lever that turns most small breaches from a spray into a detectable air-ingress event.

The network spine physically settles a decision made canonical elsewhere. Inside a scale-up domain the choice is copper vs optics. NVIDIA's GB200 NVL72 keeps the entire 72-GPU NVLink scale-up fabric on copper: more than 5,000 copper cables in NVIDIA’s October 2024 OCP description. Short passive links avoid optical conversion at their endpoints, so the engineering benefit is fewer powered optical components, with their heat, cost and failure exposure. The rack saving against an optical design needs a matched optical BOM and cannot be inferred from cable count. The catch is reach: the channel’s lane rate, insertion loss and host equalization set passive reach, and a link that crosses racks needs its own qualified copper, active-copper or optical design. The copper-vs-optics economics and the NVLink fabric itself are canonical in Chapter 8.2; the physical-layer interconnect taxonomy is in Chapter 8.9.

The scale-out (back-end) and front-end fabrics are a different physical animal: structured fiber, pre-terminated MPO trunks running from the rack to a row or end-of-row manifold, polarity-disciplined and loss-budgeted. The decision the rack owns is the boundary: where the copper spine ends and the fiber plant begins, and how the rear plane holds both without the dense copper backplane fouling the fiber breakout. Pre-terminated trunk cabling is the primary install-velocity lever, since it lets a rack land and link in hours instead of days, and Chapter 7.15 owns that story. A frame that does not reserve cable-management volume for both a copper spine and a fiber breakout forces field rework that no amount of factory integration can recover.

The fourth spine is data, and the rack is where it becomes physical. A rack record can be drawings, asset tables and port maps, or a 3D digital twin of the rack and the hall. Either way, every device is mapped to a U/OU position, every port to its peer, and a physical-layer telemetry feed (power per phase, coolant flow and temperature, leak-sensor state, busbar current, per-tray draw) streams from the rack into the model. The discipline the rack owns is making the physical object legible: asset and port mapping accurate enough to direct a remote-hands technician to the exact tray and the exact QD, and a twin faithful enough to simulate capacity, thermal and cabling decisions before steel moves. A hall with thousands of liquid-cooled racks has tens of thousands of quick-disconnects or more. Accurate geometry, connectivity and telemetry mappings are required to reason about where the next leak, thermal-margin breach or stranded U of capacity will appear.

The line between this chapter and operations is clean. The physical-layer twin (geometry, asset and port mapping, sensor wiring) is a rack-integration deliverable and belongs here. The operational DCIM (alerting, predictive maintenance, agentic ops, the run-time observability that consumes this telemetry) is canonical in Chapter 14.2, and the failure-rate data the telemetry exposes is in Chapter 14.3. The rack's job is to be instrumented and mapped at integration time; operations' job is to act on what that instrumentation reports. A rack that ships without an accurate physical record and a wired telemetry plane is a rack the fleet cannot see, and that is where the next undiagnosed leak or thermal breach lands.

The rack is integrated, not assembled: the four spines are co-designed against one frame rather than independently specified and hoped to fit. The frame is the first decision and the most durable, chosen against the workload and the density ramp, not the existing hall. A single integrator has to arbitrate the rear plane. The wet-vs-dry shipping fork trades commissioning speed against freight risk and field serviceability. The digital twin must be wired and mapped at integration time so the fleet can see a 132 kW object with dozens of coupling points. A frame chosen well lets every downstream subsystem land cleanly; a frame chosen wrong strands the floor, the power, the cooling and the cabling together.

Check each heat-removal path on its own. The electrical margin is 132 − 120 = 12 kW and the liquid margin 120 − 100 = 20 kW, but the hall removes only 18 kW of room air against the rack's 20 kW, a 2.0 kW deficit. Coolant rise is liquid duty over mass flow times specific heat, 100 / (2.0 × 4.18) ≈ 12 K, so the return is about 52 °C, inside the 55 °C limit. The rear clearance is 0.10 m short of the 0.90 m the service sweep needs. On paper the rack releases in week 14 (the last interface, week 12, plus two weeks of testing), but schedule float cannot waive a failed thermal or access interface: both fixes must land by week 12, and fixing them in week 15 moves release to week 17.

Hold the release even though electrical and liquid capacity are spare. Add verified room-air removal and clear the real service sweep, or obtain a different complete OEM profile; do not invent a lower-power mode by scaling heat splits. Record voltage, return, ground and protection, fluid chemistry, pressure and QDs, point loads, route, and fabric and management ports alongside these arithmetic checks, then carry the dated enabling works into the integrated schedule.