The DC Power Revolution: 48V → ±400V → 800V & Disaggregated Sidecar Power

The data-center power chain used to be an argument about efficiency at the margin: a percentage point of UPS loss here, a transformer K-factor derate there. The AI rack changed the units. If a rack's whole load rode a 48 V bus, a 40 kW H100 rack would draw roughly 830 A and a 132 kW GB200 NVL72 about 2,750 A. A GB300 NVL72 would draw about 2,800 A at its 135 kW TDP and 3,200 A at its 155 kW peak (Lenovo LP2357). A VR200 NVL72 at 188 kW Max Q or 228 kW Max P would draw about 3,900–4,750 A, and a ~600 kW Kyber-class rack (NVIDIA targets H2 2027; SemiAnalysis reported 2028 in July 2026) about 12,500 A. Read these as what the whole load would draw on that bus, not as measured bus currents. Even so, the connector, routing and heat penalties grow with current, and NVIDIA estimated in May 2025 that a 1 MW rack on a 54 V busbar would need up to 200 kg of copper. Current, not voltage, is the constraint the DC power revolution exists to relieve.

The revolution unfolds as a chain of decisions. First, whether to raise the bus voltage at all, and the threshold below which you should not. Then which DC voltage to standardize on: ±400 V or 800 V, a choice driven as much by supply chain as by physics. Then where the conversion lives, inside the IT rack or in a disaggregated sidecar, and how far you collapse the chain, down to a solid-state transformer that integrates MV-to-DC conversion in one package. The new engineering waits at the end: protecting and grounding a high-voltage DC bus that has no current zero-crossing to help the breaker. And for a large share of 2026 inference halls, AC still wins. Chapter 4.11 is the canonical home for protection and grounding, and Chapter 4.4 engineers the SST. This chapter makes the architectural decisions that determine whether you ever need them.

Start from the one equation behind everything downstream. For a fixed power P delivered at voltage V, current is I = P/V and conductor loss is I²R. Loss scales with the square of current, so it scales with the inverse square of voltage. Raise the distribution voltage 8x and, for the same delivered power, current drops 8x and conductor loss drops 64x. Put the other way, you carry the same power through a fraction of the copper. That inverse-square penalty is what forces the voltage up as the rack roadmap climbs.

The same arithmetic checks a vendor's headline. At equal current in each current-carrying conductor, a two-wire 800 VDC circuit carries 800·I, against √3 × 415 × I ≈ 719·I for a three-phase 415 VAC circuit at unity power factor: about 11% more power. Per current-carrying conductor the gap is wider, 400·I against about 240·I, or about 1.7×. NVIDIA's October 2025 article claims 157% more power through the same wire gauge for a three-wire DC feed (POS/RTN/PE) against four-conductor 415 VAC, and its May 2025 article put the same shift at ~85%. Neither article publishes the gauge, ampacity or power factor behind its figure, so do not size copper on either. Copper savings also come from lower current for the same power and from fewer conversion stages, so compute your own current and loss from your conductor count and route.

The copper wall is the point where a rack's low-voltage DC busbar runs out of current and thermal rating, and it moves with the busbar. OCP's MGX 1.2 specification (NVIDIA's contribution, revision 1.2.0, effective October 6, 2026) supports racks up to 250 kW on a 48 VDC liquid-cooled busbar rated at 5,000 A. That is one specific architecture, not a universal low-voltage ceiling. NVIDIA's DGX Vera Rubin NVL72 rack carries 54 VDC on a liquid-cooled busbar fed by four 110 kW power shelves, each supplied at 415–480 VAC. The shelf Flex builds for Vera Rubin NVL72 matches that 110 kW rating and delivers 52 VDC at full load (datasheet dated June 1, 2026). Like NVIDIA's figure, it rates one shelf, not the whole rack. Measured against the 250 kW MGX 1.2 ceiling, the 188 kW Max Q and 228 kW Max P operating profiles OEMs publish for Vera Rubin NVL72 fit under it. NVIDIA's DSX reference design plans the same cabinets at 330 kW TDP as the facility basis for power and cooling, which sits above it. Kyber, at roughly 600 kW a rack, lands at more than twice that ceiling. At 48–54 V a rack that size would pull well over 10,000 A. That current is what drove NVIDIA to 800 VDC for Kyber in May 2025, more than a year before MGX 1.2 took effect.

So the first fork is whether your rack roadmap outgrows the busbar you can buy within the depreciation life of the building, with one feed lost and with service access. Read the busbar's continuous current and thermal rating with one feed lost, not its nameplate, and check it against the rack configuration you are buying. Past that rating, compare a higher-current low-voltage design with high-voltage DC on route loss, insulation and service requirements. If your existing AC interface can carry the load and survive a lost feed, keeping it avoids stranding switchgear and PDUs; weigh tendered losses and replacement costs before you reopen the choice at the next refresh. → density wall in Chapter 5.1; the rack-power roadmap in Chapter 4.1.

Once you have decided to raise the bus, the next fork is the rail and grounding topology. In 2025–26 the industry split into two camps that are converging on a shared answer from opposite directions. It is the chapter's central architectural fork.

Bipolar ±400 VDC: an 800 V rail-to-rail topology with a midpoint. The OCP Mt. Diablo specification (formerly Diablo 400; final 1.0.0, effective October 8, 2026), co-authored by Google, Meta and Microsoft, is built around a bipolar ±400 V bus that the spec now calls differential 800 VDC. Two rails at +400 V and −400 V sit about a grounded midpoint, which gives an 800 V rail-to-rail span. The midpoint bond sets nominal 400 V pole-to-earth references, and an HRG first fault can shift them. The main reason is procurement. Google told OCP EMEA 2025 that 400 VDC 'allows us to leverage the supply chain established by electric vehicles'. The EV industry built a mature, high-volume supply chain around the 400 V class, so 400 V-class film capacitors, automotive connectors, fuses and contactors are candidate parts, and 650 V GaN FETs fit stacked or multilevel converter stages. Each part still needs checking against the actual continuous voltage, transients, fault interruption, creepage and service duty; an EV label does not carry installation approval. Standardizing at 400 V lets the data-center industry ride the EV supply chain instead of building a new high-voltage component ecosystem. The cost you accept is a bipolar topology: two rails, a midpoint to ground and monitor, and a balancing question. That topology has data-center precedent at lower voltage. 380–400 VDC plants with DC UPSs and midpoint-grounded buses have run in telecom and data centers since 2012, including ABB's 1 MW, 380 VDC installation at Green's Zurich-West data center (2012) and NTT's 380 V rollout (Chapter 4.1). The megawatt rack and the 800 V rail-to-rail span are what the AI generation adds.

Unipolar nominal 800 VDC: a different rail and grounding topology in the same rail-to-rail class. NVIDIA's 800 VDC reference architecture targets the ~600 kW Kyber-class rack, with roadmap headroom toward ~1 MW, on a unipolar 800 V bus delivered ideally from medium voltage through one conversion. The case for it is that 800 V at the rail minimizes current and copper for the largest racks and puts the whole facility on one number, from the solid-state transformer to the rack inlet. The cost is that 800 V sits above the comfortable range of EV-grade 400 V-class parts. 1,200 V-class SiC devices are one candidate for a two-level stage across the full span, and the switching topology sets the actual device stress. Connectors and breakers still need checking against the actual continuous voltage, transients and fault duty.

In practice the two camps reconcile, because a bipolar ±400 V distribution is an 800 V rail-to-rail system. The ecosystem (Eaton, ABB, Schneider, Vertiv, Siemens, Delta) is building to a common 800 V-class interface that accommodates both bipolar ±400 V and 0–800 V outputs. In 2026 the convergence became explicit and published. OCP's Power Distribution sub-project published an LVDC white paper (v1.0, March 2026; v1.1.0, 2 September 2026); ABB co-leads the sub-project, and Google, Vertiv, Delta, Schneider, Siemens and UL Solutions are among its workstream leads. Google, Microsoft and NVIDIA wrote the first Solid-State Transformer Specification (Rev 0.3.0, effective 22 June 2026) and describe 800 VDC as one open architecture with two coexisting deployment paths. An LVDC sidecar power rack converts existing 480 VAC locally (the Mt. Diablo lineage; a "Mt. Diablo 2.0" for native 800 V is forthcoming) and is the fast path into today's AI factories. Direct MVAC→800 VDC through MW-scale transformer-rectifiers or SST skids is the endgame. More than 80 partners, manufacturers and infrastructure companies among them, are building to the specs (OCP joint blog, 2026-08-11). NVIDIA's own product timeline matches: a hybrid MGX-compatible 800 VDC power rack in H2 2026, and native 800 V with Kyber, which NVIDIA targets for H2 2027. → the SST that feeds either bus in Chapter 4.4.

The second architectural decision is orthogonal to voltage and at least as consequential: where does the AC→DC conversion physically live? The conventional answer is in the IT rack, in shelves of rectifiers that occupy rack units compute could otherwise use. The disaggregated answer, embodied in Mt. Diablo, pulls the rectification out of the IT rack into a dedicated sidecar power rack beside the compute racks in the same row. The sidecar is full of power shelves. It converts facility AC to the high-voltage DC bus and feeds one or more adjacent IT racks over a DC busbar or a set of HVDC cables. Take the output count, connector, current and fault boundary from the Mt. Diablo revision your vendor builds to. Version 1.0.0 (§8.1.3) rates each output protection and control module at up to 400 kW and feeds the IT rack over 50 kW or 100 kW cables, as many as the load needs. It does not fix the 16 × 50 kW arrangement that has been reported. Inside the IT rack, a DC-to-50 V shelf steps the sidecar's output down to the Open Rack V3 (ORV3) busbar, so the trays keep their 50 V interface. Meta's open ORV3 HVDC-LVDC 100 kW shelf specification (1.0.0, February 2026) takes ±400 VDC on two cords through six 18 kW PSUs. Delta (90 kW, 800 VDC to 50 V, up to 98.5% efficient per Delta) and LITEON (95 kW, for Vera Rubin NVL72) showcased such shelves at OCP in October 2026 without availability dates.

Disaggregation can decouple the power-conversion lifecycle from the compute lifecycle. Rectifiers and DC-DC stages are long-lived and improve incrementally, while accelerators churn on a ~2-year cadence. An in-rack compute refresh can keep compatible power shelves, but a change in capacity or in voltage, mechanical, control or protection interfaces can force their replacement. A sidecar frees compute-rack space. According to Mt. Diablo 1.0.0 (§4.2), one power rack can serve several generations and SKUs of IT rack. That holds only while the power rack has enough output capacity for their loads and its voltage, polarity, grounding, control and protection interfaces still match theirs. The cost is a row-level architecture. The sidecar consumes floor area and aisle space, the DC interconnect between sidecar and IT rack becomes a new failure domain and a new connector-standardization problem, and redundancy is reasoned about at the sidecar-feeds-N-racks level, not per rack. → busway/PDU baseline and the ORV3 48 V bus this extends in Chapter 4.6; rack BBU placement in Chapter 4.5.

Compare direct MV-to-DC with transformer-plus-rectifier conversion using the common-boundary comparison in Chapter 4.1. Retain every downstream conversion and auxiliary load: an SST does not remove rack point-of-load conversion or automatically provide outage energy. Ask each supplier for the SST's internal topology and whole-package efficiency, because one package can still contain several conversion stages.

The procurement fork is concrete. ETH Zurich's INTELEC 2025 keynote (October 13, 2025) shows a 400 kW, 13.2 kVAC to 800 VDC industrial prototype at 98% efficiency. It comes from a US DOE project (2018–2021; Ch. Zhu, 2021), and the keynote reports the figure without an underlying test report. The same keynote frames 98–98.5% as today's state of the art and 99% as the next target. DG Matrix, Amperesand and Heron Power each claim ~98.5% for commercial units at pre-production scale. Tier-1 suppliers have now committed too. On August 14, 2026 Siemens and Reinhausen announced that they are developing, and will industrialize, a modular SST for grid voltages up to 36 kV with a galvanically isolated 800 VDC output. On September 21, 2026 ABB launched Infinitus, a source-to-rack DC portfolio built around its own SST; ABB expects a number of main components to be produced within twelve months and the first DC-native sites on the full portfolio within two to three years. Certification has not caught up. UL Solutions opened a UL 2877-based certification program for medium-voltage solid-state power units on September 24, 2026, but no data-center SST had a confirmed UL certification as of October 19, 2026. DG Matrix’s June 17, 2026 announcement targeted UL certification by the end of Q2, and its releases through October 13 do not report it. So the fork is timing, not principle: procure the integrated MV-to-DC SST package now and accept first-mover risk on a component without confirmed certification, or stage it. Carry the SST only if, by the committed delivery date, its certification is confirmed and it has passed MV protection, isolation, output grounding and service tests. Otherwise keep conventional conversion and document an interface for a future SST. Even a certified SST will need a compatibility check before it can replace that plant. Chapter 4.4 owns converter qualification.

Conversion is the easy part. Protection is hard because direct current behaves nothing like alternating current at a fault, and most installed protection practice assumes AC. Protection, not conversion, is where a DC bus becomes a safety case rather than a spreadsheet line.

No zero-crossing. An AC fault current passes through zero 100–120 times a second, and a mechanical breaker uses those zeros to interrupt the fault. That is an opportunity, not a guarantee: the arc restrikes if dielectric recovery across the parting contacts is too slow. A DC fault current has no such zero. The arc wants to sustain itself, so interrupting it takes equipment that forces a current zero or absorbs the energy outright. An arc-flash study, not the voltage number, settles which of the two events is more dangerous at a given voltage. One option is the solid-state circuit breaker (SSCB), a semiconductor interrupter such as a SiC design that opens rapidly to limit additional source-fed fault energy, often paired with a mechanical disconnect for galvanic isolation. DC-rated fuses and electromechanical or hybrid devices are alternatives when their voltage, prospective-current and clearing characteristics meet the study. Charged capacitors contribute their stored energy regardless. SSCBs are a different device class from the molded-case breakers AC designers know, with different coordination behavior, so the protection-coordination study has to be redone in the DC domain.

Arc-flash and touch safety. Incident energy on a DC bus depends on available fault current, arc behavior, clearing time, enclosure and working distance. No AC study transfers across, so recompute arc-flash analysis and PPE boundaries with a DC method. On a bipolar ±400 V bus, an ideal solid midpoint holds each conductor 400 V from earth in normal operation, whereas an end bond puts the opposite pole at 800 V. Study HRG and isolated outputs separately for first-fault current, healthy-pole stress, detection and clearing; the nominal reference alone does not establish touch safety. Grounding and isolation are where ±400 V and 800 V diverge. On a bipolar ±400 V bus the reference is a grounded midpoint, and the two rail voltages must stay balanced about it under continuous monitoring. First-fault behavior on a unipolar or deliberately ungrounded (IT-style) 800 V bus depends on the actual bond, isolation, capacitance, leakage and protective controls. Specify continuous insulation/ground-fault monitoring and isolation that detect the first fault and run the studied protective response before an opposite-pole fault creates a short. This ground-fault problem on ungrounded and high-resistance-grounded ±400/800 V systems is the novel piece, and Chapter 4.11 is its canonical engineering home. Treat this section as the architectural flag: a high-voltage DC bus needs a team that can run DC protection, grounding and isolation procedures.

Equal full-span voltage means equal ideal load current, not equal fault behavior. I = 200,000 W / 800 V = 250 A in either full-span connection. The isolated capacitor starts with E = ½CV² = ½ × 0.020 F × (800 V)² = 6.4 kJ. Through the resistor, V(t) = 800e^−t/(RC), so reaching 10 V takes 3,000 Ω × 0.020 F × ln(800/10) = about 260 s, inside the 300 s window. The resistor starts at 800²/3,000 ≈ 210 W and absorbs almost the full 6.4 kJ, so check its pulse and continuous thermal ratings separately.

The window breaks at 300/[3,000 × ln(80)] ≈ 23 mF: any bank at or above that misses it. At 40 mF, discharge takes about 530 s, so lengthen the interlocked wait or use a different discharge network. The 20 mF case passes this screen, but service release still waits on tests of source isolation, discharge-path failure, voltage verification and interlocks. A first earth fault changes rail-to-earth stress according to the actual bond, and the capacitor calculation neither rates a breaker nor proves first-fault safety. Chapter 4.11 owns detector and earthing selection, and the rack supplier owns the Chapter 7.12/7.13 interface. No automotive-component analogy substitutes for testing the installed system.

The DC revolution is real and inevitable at the top of the density range, and irrelevant to a large share of the 2026 fleet. Migration is a coexistence problem, not a flag day. Most operators will run mixed estates: AC busway feeding 48 V racks wherever the deployed rack class stays inside the 48 V limits, and DC distribution (±400 V or 800 V) reserved for the Kyber-class rows that do not. Rack kW and the rack configuration you buy decide that, not whether the row is labeled training or inference; frontier inference deploys the same NVL72-class racks as training (Chapter 4.6). The two architectures share a facility, a substation and an MV distribution, and diverge only in the last conversion stages. The scope of that divergence depends on the path. An AC-fed sidecar is a row-level decision. A direct MVAC→800 VDC power block feeding a whole data hall is a hall-level decision. That block sits upstream of the rows and comes with its own protection and storage interfaces.

AC still wins, decisively, in four cases. The rack you are buying stays inside its AC current, thermal and failure limits, below the copper wall. The build is a retrofit of an AC-distributed hall, where ripping it out for DC strands working switchgear and PDUs. The operator lacks DC protection and grounding skills and cannot build them on the project timeline. Or the schedule cannot absorb the thinner DC vendor pool and the pending certifications. Latency-bound inference often lands in existing AC-distributed metro capacity, but that is a siting choice that happens to keep AC, not a reason to choose it. DC wins when a DC configuration solves a demonstrated rack-current, routing or loss problem within the building’s life, whether the dense workload is training or inference, and the operator is building greenfield with the engineering depth to take on the new protection regime. The rack configuration you are buying and the density ramp decide the call; the elegance of the power architecture does not. → workload-driven scoping in Chapter 1.1; the density wall that triggers all of this in Chapter 5.1.