Appendix E

In this chapter · 7 sections

Term help

Terms in this chapter (164)

Glossary, Phase-Gate Timeline & Learning/Community Map

This appendix gives you three reference layers: a glossary of the terms of art, a worked dependency-schedule exercise, and the primary sources and communities that keep a project team’s decisions current.

What you'll decide here

Use the glossary as a decoder ring (full A–Z at /glossary). When a definition falls short, jump to the chapter in column three.
Compute float for each phase gate against Chapter 2.1’s network, then test whether a late building or an early transformer moves the first productive run.
Swap the illustrative month allowances for your utility’s milestones and equipment quotes. Retrofits and colocation still need land, permits and construction where contracts require them.
Pick one certification track per discipline on your team, calendar two or three anchor conferences, and follow feeds so primary sources correct this guide's figures.

This appendix is the reference layer for the rest of the guide, and it does three jobs. First, the glossary: four thematic tables that resolve the terms of art the body chapters lean on hardest, with the site's full A–Z decoder at the glossary. The tables run from efficiency ratios (PUE, WUE, ERF) through utilization metrics (MFU, MBU, goodput) to fabric and packaging vocabulary (NVLink domain, CoWoS, HBM, RoCE) and program-management terms (SU, ETTR, phase gate). Each entry names the chapter that owns the full treatment, so the glossary doubles as an index. Second, the phase-gate timeline: illustrative package durations from raw land to a live cluster, with criticality calculated from Chapter 2.1’s dependency network. A common scoping error is treating parallelizable work as serial and serial work as parallelizable. Third, the learning and community map: the certifications, conferences and feeds that let a practitioner keep this material current after the ink dries.

None of it is meant to be read front to back. It is a lookup layer, and the tables are dense on purpose.

Glossary — efficiency, utilization & thermal metrics

The vocabulary is split across four thematic tables so each stays scannable. This first table covers the facility-efficiency and workload-utilization ratios. Chapter 15.1 builds the canonical definitions and the post-PUE metric stack, Chapter 0.3 anchors the utilization metrics, Chapter 14.1 defines goodput, and Chapter 12.2 prices it against availability.

Glossary I — efficiency, utilization & thermal metrics

Term	Definition	Canonical chapter
PUE — Power Usage Effectiveness	Total facility energy divided by IT energy over the same period and boundary. The theoretical ideal is 1.0. A power ratio at one operating point is not annual PUE, and PUE says nothing about IT-side efficiency.	15.1
WUE — Water Usage Effectiveness	Liters of site water used per kWh of IT energy, on a defined boundary. Separate withdrawal, discharge and consumptive loss. Where evaporative rejection lowers cooling electricity, lower PUE comes with higher site WUE.	15.1, 15.4
ERF — Energy Reuse Factor	Fraction of facility energy exported as useful heat (district heating, for example). Higher is better, unlike the facility ratios PUE, WUE and CUE.	15.1, 15.5
REF / CUE — Renewable Energy / Carbon Usage	REF: renewable share of supply. CUE: kg CO2e per kWh of IT energy. The carbon companions to PUE.	15.1, 15.3
ITUE / TUE — IT / Total Usage Effectiveness	ITUE moves the boundary inside the server (fans, VRMs, PSUs). TUE = PUE × ITUE, the true facility-to-transistor ratio.	15.1
MFU — Model FLOPs Utilization	Useful model FLOPs divided by the matching dense peak over the same training window. State the model, precision and FLOP convention; exposed collectives and stragglers lower the result.	0.3, 13.9
MBU — Model Bandwidth Utilization	Achieved memory bandwidth divided by peak, for memory-bound decode inference. It is the MFU analog when HBM bandwidth, not FLOPs, is the bottleneck.	0.3, 10.11
Goodput	Useful work delivered within the declared quality and service limits; as a time fraction, the share of wall-clock time that advances the job. MFU, which measures utilization of peak FLOPS, is a different metric; so are raw throughput and facility availability.	14.1, 12.2, 10.11
ETTR — Effective Training Time Ratio	Productive training wall-clock divided by total elapsed wall-clock. It folds in interruptions, checkpoint overhead and restart loss, and is the goodput metric for training.	12.2, 9.4
Tokens-per-joule	Inference tokens delivered per joule at a defined energy boundary. Comparing vendors needs a matched model, quality, precision, context, concurrency and latency SLO.	15.1, 7.10
$/GPU-hr	Cost or price per GPU-hour, so say which: installed, available, productive or billable. For build-vs-rent, align capex, power, cooling, staff, networking and finance scope before comparing.	1.8, 7.11
$/M-tokens	Cost or selling price per million tokens; keep the two separate. Specify input and output tokens, model quality and serving SLO before testing inference revenue against cost.	1.8, 10.11
EDP — Energy-Delay Product (per op)	Energy × latency, which penalizes designs that are both slow and power-hungry. A silicon and architecture figure of merit that resists gaming on either axis alone. Do not confuse it with EDPp, the electrical design point (peak) in HPE and NVIDIA rack documents (see TDP in Glossary II).	7.10
Delta-T (coolant rise)	Outlet minus inlet temperature of the same fluid: Q = mass flow × cp × ΔT. A 10 K coolant rise is a chosen design point, not an exchanger approach. Test it against the product’s rated operating range.	5.1, 5.4
Approach temperature	The temperature difference between two different streams at a defined terminal of a heat exchanger, such as facility supply against technology supply at a CDU. It sizes the exchanger and sets how cold the technology loop can run. A CDU can carry a 10 K rise and a 3 K approach at the same time.	5.11, 5.6
NTU / effectiveness	Number of transfer units and heat-exchanger effectiveness: the sizing math for CDUs and dry or wet coolers.	5.1
CFADS	Cash flow available for debt service under the governing agreement. Reconcile cash opex, taxes, maintenance, working capital and reserve movements.	2.5
DSCR	CFADS divided by the included interest and scheduled principal for the same period. Specify the covenant and the measurement period. Its companion, the DSRA (debt service reserve account), holds cash sized in months of debt service; Appendix C's financing calculator defaults to six.	2.5

Direction is noted where a metric’s sense is not obvious. The canonical chapter owns the full derivation; the one-liner here is the bench definition.

Glossary — compute, memory & packaging

The silicon and packaging vocabulary that gates supply and density. Chapter 7.1 covers the accelerator landscape, Chapter 7.6 HBM as the binding constraint, and Chapter 7.7 advanced packaging.

Glossary II — compute, memory & packaging

Term	Definition	Canonical chapter
HBM — High-Bandwidth Memory	Stacked DRAM (HBM3E/HBM4) integrated with the accelerator package. Capacity and bandwidth constrain different workloads, and the memory and packaging supply chain can gate delivery.	7.6
CoWoS — Chip-on-Wafer-on-Substrate	TSMC’s 2.5D packaging family. It joins logic and HBM through interposer or RDL structures that differ by variant. CoWoS capacity can gate assembly, so identify the variant before applying a limit.	7.7
Interposer	The silicon (or organic/RDL) layer carrying high-density interconnect between logic and HBM in a 2.5D package. Reticle-size limits drive the move to larger and stitched interposers.	7.7
XPU	Generic term for a non-GPU AI accelerator (TPU, Trainium/Inferentia, Maia, MTIA): hyperscaler custom silicon competing with merchant GPUs.	7.4, 7.5
MoE — Mixture of Experts	Sparse architecture that activates a subset of expert sub-networks per token. It widens expert parallelism and reshapes both training fabric and inference KV-cache pressure.	1.2, 8.5
KV cache	Cached key/value tensors for attention during decode. Its size scales with context length and concurrency, dominates inference memory and drives disaggregation.	9.7, 10.11
Quantization (FP8/FP4/INT8)	Reduced numerical precision to cut memory and lift throughput: the compute-vs-accuracy lever, increasingly native in Blackwell/Rubin-class silicon.	7.10
TDP — Thermal Design Power	Vendor-defined thermal design power for a given package or rack. It informs cooling duty, but it is not automatically measured demand, electrical peak or facility provisioning power. OEM sheets give those separately: Max Q and Max P operating profiles, an electrical peak such as HPE's EDPp (electrical design point, peak) that sizes breakers and busway, and a provisioning figure. Appendix B lists them by rack.	5.1, 7.12
Power transient / load step	Synchronized GPU draw swings (idle to full across thousands of GPUs in milliseconds) that stress the power chain. Mitigated chip→BBU→BESS.	4.5, 7.12
SST — Solid-State Transformer	Power-electronics conversion with topology-specific isolation, proposed for MV-to-800 VDC conversion. OCP's SST Specification (Rev 0.3.0, effective 22 June 2026) sets the requirements; UL opened its certification program on 24 September 2026, and no certified product is named yet. Compare full-system efficiency at your operating duty, plus protection and serviceability.	4.4, 4.7
PVF	Program Vulnerability Factor: workload-dependent exposure of output to hardware faults, under a given study’s fault model and coverage.	14.3

Vendor-neutral definitions. Where a term belongs to one vendor the entry names it, because NVIDIA’s and TSMC’s dominate the 2026 deployed base.

Glossary — interconnect, fabric & networking

The network vocabulary has two tiers: scale-up (inside the coherent domain) and scale-out (across the cluster). Chapter 8.2 treats scale-up interconnect, Chapter 8.5 scale-out topology and oversubscription, Chapter 8.4 scale-out protocols and transport, and Chapter 8.6 congestion control.

Glossary III — interconnect, fabric & networking

Term	Definition	Canonical chapter
NVLink domain (scale-up domain)	The set of GPUs sharing a coherent high-bandwidth NVLink/NVSwitch fabric: 8 in an HGX node, 72 in an NVL72 rack (GB200, GB300 or Vera Rubin). NVIDIA’s planned Rubin Ultra NVL576 spreads 576 GPUs across eight racks joined by optics (roadmap, not shipping). Domain size sets the tensor- and expert-parallel ceilings.	8.2, 8.5
NVSwitch	NVIDIA’s switch ASIC that fully connects a scale-up domain. NVLink-SHARP does in-network reduction to speed up collectives.	8.2
UALink	UALink is a multi-vendor scale-up alternative to NVLink; 200G 1.0 supports up to 1,024 accelerators. AMD Helios names UALoE; Ethernet transport is implementation-specific, not inherent to UALink.	8.2
InfiniBand (IB)	Low-latency lossless scale-out fabric with native RDMA and adaptive routing. The historical default for non-blocking training back-ends.	8.4
RoCE — RDMA over Converged Ethernet	RDMA carried on Ethernet (typically lossless via PFC/ECN+DCQCN). The open, cost-driven scale-out alternative to InfiniBand.	8.4
Spectrum-X	NVIDIA’s Ethernet-based scale-out platform, which tunes RoCE for AI collectives (adaptive routing, congestion control). The Ethernet answer to InfiniBand.	8.4
UEC — Ultra Ethernet Consortium / UET	UEC issues Ultra Ethernet Transport (UET): packet spray with out-of-order delivery, packet trimming, and two congestion-control algorithms in its Congestion Management Sublayer (CMS), sender-side NSCC driven by network signals and receiver-credit RCCC. UE 1.1 (12 October 2026) adds CSIG in-band congestion signaling, programmable congestion management, in-network collectives and a Unified Local scale-up profile. Use the revision listed in Appendix A, and test the AI/HPC stack you buy against it.	8.4, 8.6
Rail-optimized / fat-tree	Rail alignment puts corresponding GPU NICs on the same rail; a fat-tree is a switching topology. Leaf and spine counts and placement decide capacity, and neither label guarantees collision-free collectives.	8.5
Oversubscription ratio	Downstream over upstream bandwidth at a defined tier or cut: 1:1 is balanced, 3:1 has three units downstream per unit upstream. Failure state and workload traffic decide how much blocking is acceptable and what it costs.	8.5
Bisection bandwidth	Minimum aggregate link capacity across a cut that splits the endpoints into equal halves, stated with direction and failure state. It bounds all-reduce traffic but is not measured collective throughput.	8.5
PFC / ECN / DCQCN	Lossless-Ethernet congestion-control mechanics: Priority Flow Control (pause), Explicit Congestion Notification, and the DCQCN tuning loop. Mis-tuned, they cause head-of-line blocking and victim flows.	8.6
CPO — Co-Packaged Optics	Optical engines placed beside a switch or compute ASIC shorten the electrical reach. For NVLink/scale-up or scale-out, trade power and reach against fault isolation, replaceable unit and repair logistics.	8.10, 8.9
NVMe-oF	NVMe over Fabrics (RoCE or TCP transport) for disaggregated storage: the placement-vs-transport tradeoff for the storage rail.	8.5, 9.1

Scale-up = tight coherent domain (NVLink/UALink class); scale-out = looser cluster fabric (InfiniBand/Ethernet class).

Glossary — facility, power, cooling & program

The building, electrical, mechanical and project-management terms. Chapter 4.1 covers power topology, Chapter 5.4 DLC, Chapter 12.2 the reliability rethink, and Chapter 2.1 the integrated master schedule and critical path.

Ride-through for a large computational load means the site stays connected during a normally cleared grid voltage sag, within a set voltage and duration curve, and draws most of its pre-fault demand back soon after (ERCOT NOGRR282: at least 90% within 2 s of voltage recovery). Transferring to backup when the source is lost is a different thing. ERCOT applies the rule to new large computational loads from August 1, 2026, SPP to large-load requests from January 15, 2026, and PJM has proposed one. NERC’s computational-load (CLO) standards passed final ballot (announced October 15, 2026) and await Board adoption and FERC approval. Its registry criteria, approved by the NERC Board on October 8, 2026, still need FERC approval. See Chapter 4.10, Chapter 4.3 and Chapter 13.6.

Glossary IV — facility, power, cooling & program management

Term	Definition	Canonical chapter
SU — Scalable Unit (reference design)	The repeatable build block (a defined MW, GPU, cooling and fabric increment) that the capacity ramp is composed of. It is the unit of design reuse and procurement. Integrators state delivery by manufacturing level: L10 a built server, L11 an integrated, tested rack, L12 a multi-rack pod tested in the factory (Chapter 7.14).	1.7, 7.14
DLC — Direct-to-Chip Liquid Cooling	Cold plates on hot components, fed by a technology loop that a CDU isolates from facility water. Choose DLC where your equipment’s heat split, airflow limits, density roadmap and facility limits require it. A water-fed rear door can bridge some air-side cases, within the rated limits of the rack and door.	5.4
CDU — Coolant Distribution Unit	A coolant-distribution assembly with specified pumps, control and interfaces. A liquid-to-liquid CDU isolates the FWS from the TCS through an exchanger; valves, sensors and topology determine leak isolation.	5.6, 5.13
RDHx — Rear-Door Heat Exchanger	A water-fed liquid-to-air door sized to the rack-and-door rating and operating range. Its coil connects to chilled or tempered water at the door. AALC/L2A is the room-air-rejecting brownfield step before full DLC.	5.3, 5.10
800 VDC	Higher-voltage DC rack distribution, in two forms: OCP’s Mt. Diablo 1.0.0 (effective 8 October 2026, formerly Diablo 400; differential 800 VDC, ±400 VDC about a midpoint; Microsoft, Meta, Google) and NVIDIA’s unipolar 800 VDC architecture. As IT racks climb from ~100 kW toward the ~600 kW Kyber-class roadmap point and 1 MW, higher-voltage DC removes conversion stages and carries the same power on less copper. Compare grounding, protection and connectors before choosing.	4.7
BBU / BESS	Battery Backup Unit (rack-level ride-through) and Battery Energy Storage System (facility-level). The chip→BBU→BESS spine absorbs GPU load transients and bridges to gensets.	4.5, 4.7
Tier (Uptime I–IV)	Uptime Institute topology classification, from Tier I (basic) to Tier IV (fault-tolerant). Tier III is concurrently maintainable. Use the classification only after you have fixed the capacity, maintenance and fault outcomes you need.	12.1, 12.2
2N / N+1	Capacity notation: N+1 adds one component beyond N; 2N provides two systems of N capacity each. Maintenance continuity and fault survival depend on paths, controls and tested states, not the count alone.	12.2
RBD / FTA / Markov / Monte-Carlo	The availability-modeling toolkit: Reliability Block Diagrams, Fault Tree Analysis, Markov state models and Monte-Carlo simulation. This is the quantitative machinery behind the nines.	12.5
Phase gate (stage gate)	A go/no-go decision point between project phases, where deliverables are reviewed and capital is released. It is the spine of the timeline table below.	2.1
IMS / critical path	Integrated Master Schedule and its critical path: the longest dependent chain of tasks, where any slip slips the whole project. Everything off the path has float.	2.1
Long-lead equipment	Items whose procurement lead time (transformers, switchgear, chillers, GPUs) drives the schedule. Order them against a frozen design basis before they bottleneck go-live.	2.3, 2.1
Commissioning (Cx) L1–L5	The five commissioning levels, from factory acceptance (L1) through component and system testing to integrated systems testing (L5 IST). They prove the facility before load.	13.1, 13.6
Speed-to-power	The time from contract to energized MW. Often the controlling constraint and a primary siting screen, though which path governs is project-specific. The two routes are grid service at a point of interconnection (POI), paced by the utility’s studies and upgrades, and behind-the-meter (BTM) generation on site.	3.2
TTFT / TPOT	Time-To-First-Token and Time-Per-Output-Token: the two latency SLOs that govern online-inference fleet sizing.	10.11
RPN	Ordinal FMEA priority S × O × D, not a failure probability. Review high severity separately.	F
UQD	Universal Quick Disconnect, OCP's open coupler specification (v2.0.0, effective September 2026); MGX 1.2 trays blind-mate on UQD-08/UQDB-08, while NVIDIA's MQD/MQDB is a separate OCP family for MGX's other couplers. Check the revision, size, materials, fluid and mating pair. “Dripless” describes rated conditions, not zero release in every state.	5.13
FWS / TCS	Facility Water System / Technology Cooling System. Name the exchanger and all four supply and return measurement points. ASHRAE ties its liquid-cooling classes (W17, W27, W32, W40, W45, W+) to the upper limit of facility-water supply temperature. The class fixes the water temperature your plant must deliver; your climate then decides how many hours dry coolers can reach it.	5.11, 0.4

The cross-discipline vocabulary that the phase-gate timeline below assumes you already speak.

The project phase-gate timeline & critical path

A greenfield AI campus’s land-to-live schedule is the longest connected path through utility service, permits, equipment, construction and cluster acceptance. Firm megawatts often govern, but the dependency network has to show it. The table sequences the program as phase gates: each package’s illustrative duration, the gate decision that releases the next phase, and the dependency that could make it critical. The last column lists candidate gates, not calculated float. A zero-float path moves the finish one-for-one until another path takes over. On a power-bound build the critical path runs through interconnection, not construction. The grid study, the utility agreement, and the substation and transformer lead time routinely dominate everything after them. So land and power are secured before design is frozen, and long-lead electrical gear is ordered the moment the design basis is signed.

Read the duration ranges as one illustrative 2026 planning scenario for a >50 MW build, not survey medians and not commitments. Rebuild them from your serving utility's milestone dates and current equipment quotes. A retrofit or colocation fit-out can reuse land, permits and construction only where those assets and permissions cover the new load. A contested interconnection or transformer queue can still control go-live, so carry each surviving obligation into the network.

Phase-gate timeline — land to go-live (greenfield, >50 MW AI campus)

Phase	Illustrative allowance	Gate decision (what releases the next phase)	Candidate dependency
0. Scope & site search	2–6 months	Workload profile, capacity ramp, and design basis signed; target market and shortlist approved.	Defines the released scope
1. Land control	1–4 months	Site optioned/acquired; zoning and entitlement path confirmed; environmental Phase I clear.	Controls site-specific starts
2. Power / interconnection	12–48 months	Executed interconnection agreement and firm-capacity / energization date. Can bind when the utility service path controls the linked schedule.	Utility date can bind
3. Permitting & entitlement	6–18 months	Building, environmental, water and air permits issued. Often overlaps power but can become the binding gate.	Permit release can bind
4. Design (concept → DD → IFC)	6–12 months	Issued-for-construction documents; design basis frozen so long-lead gear can be ordered.	Package freeze gates orders
5. Long-lead procurement	In parallel: transformers ~128 to 160+ weeks, switchgear ~44 weeks (Wood Mackenzie, 2025–26). Replace with current quotes.	POs placed against the frozen design; transformers, switchgear and chillers ordered early to de-risk the schedule.	Delivery can bind installation
6. Construction (shell + fit-out)	12–24 months	Substantial completion; building, electrical and mechanical infrastructure ready for commissioning.	Readiness gates integration
7. Commissioning (L1–L5 IST)	3–9 months	Integrated Systems Testing (L5) passed; installed systems proven with load banks and fixtures before revenue service. Where the region binds ride-through (ERCOT NOGRR282, SPP), show the computing load stays connected inside the required voltage and duration limits, tested apart from source-loss transfer (Chapter 13.6).	Accepted plant gates live IT
8. Cluster bring-up & burn-in	1–4 months	GPU node burn-in, fabric validation and reference-training/benchmark acceptance complete.	Accepted cluster gates service
9. Staged ramp & go-live	1–3 months	Staged power/load ramp to full; handover to operations; SLA clock starts.	Contractual end milestone

Durations are one illustrative 2026 planning scenario, not survey medians. Phases overlap, so the column does not sum to the 24–60 month land-to-go-live range this scenario implies. The candidate dependencies need a linked schedule before you call any row critical. See Chapter 2.1 for the integrated master schedule and Chapter 3.2 for the interconnection mechanics that dominate it.

Illustrative — stated assumptions

A building slip changes the controlling path. Reuse the Chapter 2.1 Cedar network. Week zero is release. The utility is ready at week 44, factory duration is 40 plus 4 for shipping, and the building is ready at week 42. Installation takes 6 weeks after the dock and the building. Facility acceptance takes 4 after the utility and installation. IT is delivered at week 46, racking takes 2 after IT and the building, and validation takes 6 after acceptance and racking. These are unsupported teaching assumptions, not market lead times. Links are finish-to-start with zero lag and unlimited resources, which matches the deterministic case in Chapter 2.1; its disruption probabilities are excluded here. Change building readiness to week 47 to cross the week-44 dock dependency, and assume a week-62 customer deadline to test the resulting slip. The case record contains every input and calculation.

The owner has to decide whether expediting the transformer can still protect the customer date. The base network finishes in week 60. With the building ready in week 47, the dock still lands at 40 + 4 = 44. Installation finishes at max(44, 47) + 6 = 53, and facility acceptance at max(44, 53) + 4 = 57. Racking finishes at max(46, 47) + 2 = 49. Productive readiness is max(57, 49) + 6 = week 63, one week past the assumed deadline. An earlier transformer buys no recovery while the building governs installation.

Give the construction lead a week-46 building-release milestone instead. Installation and acceptance then finish in weeks 52 and 56, racking in week 48, and productive readiness in week 62, which flips the deadline decision. At week 44 or earlier the dock path governs again and the finish stays at week 60. Confirm that each predecessor has actually finished before promising either date: energization alone does not finish acceptance or workload validation. Chapter 2.1 owns the network and the probabilistic method; GAO’s Schedule Assessment Guide supplies the scheduling evidence discipline.

Where the schedule actually lives or dies

Three rows dominate the spread. Power (Phase 2) can bind when the host utility’s service path controls the linked schedule. Its executed tariff election, study and upgrade scope, and agreement milestones and remedies tell you more than any portable national duration. Long-lead gear (Phase 5) is where schedules slip quietly. Wood Mackenzie’s 2026 figure for US substation transformers is above 160 weeks; its Q2 2025 survey had power transformers at ~128 weeks. Reuters (July 2026) reported GSU waits passing 160 weeks by Q1 2026. Wood Mackenzie’s Q2 2025 survey put switchgear at ~44 weeks on average, without giving a voltage class. Place those orders the moment IFC documents land and the design basis is frozen, so procurement runs alongside construction. Commissioning (Phase 7) is the phase teams most often compress to hit a go-live date, and an unfinished L5 integrated systems test moves the discovery of interface and sequence defects into the first months of live load. Which phases are actually critical follows from your own dependency logic, durations and float, not from a phase’s name. → master schedule mechanics in Chapter 2.1, interconnection in Chapter 3.2, commissioning in Chapter 13.1.

Learning & community map — certifications

Certifications split by discipline, and no single credential covers an AI-data-center engineer. Strong teams hold a spread across facility design, operations, and the network/compute stack. The table gives each credential, its issuer and the role it maps to. Use it as a hiring and development reference, not a gate: deployed expertise in this field still outruns any certificate.

Three more credentials cover what the ladder below misses. ACG’s Certified Commissioning Authority (CxA) suits the commissioning lead who runs L1–L5. BICSI’s RCDD (Registered Communications Distribution Designer) covers the structured cabling and pathways behind the fabric. Uptime Institute’s Accredited Operations Specialist (AOS) is for the people who run the facility once it is live.

Certification ladder

Credential	Issuer	Maps to role / domain
ATD — Accredited Tier Designer	Uptime Institute	Licensed facility design engineers, engineers of record and design-management project managers. Uptime’s design-side Tier credential. It counts when an owner wants Tier Certification of the Design Documents or of the Constructed Facility. ATS covers operations and non-licensed roles.
ATS — Accredited Tier Specialist	Uptime Institute	Operations and facility staff managing and maintaining to Tier criteria, plus architects, consultants, contractors and non-licensed design staff. A Tier credential alongside the ATD.
CDCDP — Certified Data Centre Design Professional	CNet Training, an Uptime Education company (BTEC-accredited)	Multidisciplinary facility-design competency; the design rung of the CNet ladder.
DCDC — Data Center Design Consultant	BICSI	BICSI’s design credential, examined against ANSI/BICSI 002. Its issuer, eligibility and curriculum are separate from CNet’s CDCDP.
CDCMP / CDCEP	CNet Training (Uptime Education)	Data Centre Management / Energy Professional; operations leadership and efficiency engineering.
CDCP / CDCS / CDCE	EPI	Certified Data Centre Professional → Specialist → Expert, a tiered facility-operations ladder.
PE (Electrical / Mechanical)	State licensing boards (US) / equivalents	The statutory license to stamp design documents; foundational for Phase 4 sign-off.
NVIDIA-Certified (NCP/NCA, networking & AI infra)	NVIDIA	GPU-cluster and fabric engineers; CUDA/NCCL, InfiniBand/Spectrum-X, and DGX/SuperPOD operations.
Vendor network tracks: Cisco CCNP; Arista ACE; Juniper JNCIP	Cisco / Arista / Juniper	Scale-out fabric engineers who build and tune RoCE and lossless-Ethernet AI back-ends.
OCP-aligned training	Open Compute Project community	Open-hardware rack/power/cooling literacy (Open Rack, Mt. Diablo ±400 VDC, ORW).

Vendor-neutral facility credentials first, vendor and network credentials second. Match the credential to the role, then ask for work product from the matching chapter: a checked electrical state schedule, a thermal interface sheet or a fabric acceptance trace.

Learning & community map — conferences & feeds

Two final tables. The conference calendar is where you calibrate against the field: hardware roadmaps break at OCP and GTC, facility practice at DCD and 7x24, and network practice at the OCP networking tracks and vendor summits. The feeds help you spot changes between editions, but verify quantitative decisions against primary sources: independent analysis (SemiAnalysis), facility-industry reporting (DCD, Data Center Frontier), the standards bodies themselves, and the operator engineering blogs that publish primary reports from named production fleets.

Three fields have their own venues outside this calendar. News in AI optics (1.6T modules, LPO and CPO) breaks at OFC, held each March (2027: March 7–11, Los Angeles). Thermal guidance moves at ASHRAE’s Winter and Annual Conferences (2027: Chicago and New Orleans), where TC 9.9 meets. NERC’s Large Loads Working Group is where grid rules for large loads take shape. EPRI’s DCFlex program is a set of field demonstrations that test how much a data center’s load can flex (Chapter 15.8).

Conference calendar — the anchor events

Event	Cadence / dated edition and issuer program	Why it is on the calendar
OCP Global Summit	Annual Global Summit; next edition October 4–7, 2027, Moscone Center, San Francisco (moving from San Jose). Regional OCP summits (EMEA, APAC) have separate programs.	Where hyperscaler-grade open hardware breaks: Open Rack, 800 VDC / Mt. Diablo, cooling and networking working groups.
NVIDIA GTC	Annual main GTC; 2027: March 15–18, San Jose. NVIDIA’s FAQ says March 14–18, so confirm the dates before booking travel. Regional GTCs have separate programs.	The accelerator/roadmap keynote that sets the density-ramp expectations the rest of the industry designs against.
DCD>Connect (regional series)	Multiple editions (NYC, London, Virginia, APAC); official program. Select the event year before booking.	The facility-operator and capital-markets gathering; siting, power, cooling, and build-out practice.
7x24 Exchange	US spring and fall conferences; fall 2026: October 25–28, San Antonio.	Mission-critical facility operations, commissioning and reliability: the Cx/operations community.
Datacloud / Data Centre World	Annual, separate series: Datacloud: June 2–4, 2027, Cannes; Data Centre World London: March 10–11, 2027; other DCW editions have separate programs.	European and global colocation, investment, and infrastructure deal-making and design practice.
DesignCon	Annual; February 2–4, 2027, Santa Clara.	Signal/power integrity and high-speed interconnect engineering: the physical-layer fabric community.
Hot Chips / ISSCC / SC	Annual academic/industry programs, separately organized: Hot Chips, ISSCC and SC26.	Silicon architecture (Hot Chips, ISSCC) and HPC/AI supercomputing (SC) — the upstream compute and packaging research.

Dates identify editions, not permanent windows. Match the discipline to the role; the why-go column is the calibration a feed cannot supply.

Feeds to follow — keep the numbers current

Source	Type	What it is good for
SemiAnalysis	Independent analysis (paid)	Analyst $/GPU-hr models, CoWoS/HBM supply-chain work, rack teardowns and fabric economics. Inspect the method and get supplier data before using it for procurement.
Data Center Dynamics (DCD)	Industry news	Facility builds, power deals, interconnection news, and roadmap reporting across the global market.
Data Center Frontier	Industry news	US-focused reporting on facility engineering, power architecture and the cooling transition.
The Next Platform / The Register (on-prem)	Technical journalism	Systems-level AI-infrastructure and interconnect analysis with an engineering bent.
LBNL (Berkeley Lab) — Queued Up et al.	Primary research	Authoritative interconnection-queue, grid and data-center energy studies: the source behind the power figures.
Uptime Institute (research & blog)	Standards / research	Tier standards, outage analyses and the annual data-center survey. Carry the surveyed population, definitions and limitations along with any figure you quote.
OCP / UEC / UALink / OIF (standards bodies)	Primary specs	The authoritative spec text for open rack/power/cooling and AI-fabric standards. Read the spec, not the summary.
Operator engineering blogs (Meta, Microsoft, Google)	Operator primary reports	RoCE-at-scale, checkpointing, fleet-reliability and cooling practice, published from real production clusters.

Primary and independent sources rank above vendor marketing. These are the feeds that correct this guide between editions.

How to keep this appendix from going stale

Every figure in this guide has a half-life. Density numbers move each accelerator generation, interconnection-queue medians move with each ISO filing, and lead times move with the transformer market. A reference like this stays useful through the habit that keeps the guide current: cite the source and as-of date for every load-bearing number, and re-check the ones that gate a decision before you act. The feeds table is the maintenance plan. When this guide and a primary source disagree, the primary source wins. A glossary entry's canonical chapter is where you learn why the number moved, not just that it did.

Read the four layers together: the glossary tells you what a term means, the canonical chapter why it matters, the phase-gate timeline when the decision is due, and the community map where to check that the answer still holds. Apart, each ages; together, they keep the reference honest a year after it ships.

The metrics in Glossary I are derived in Chapter 15.1 (efficiency stack), Chapter 0.3 (utilization) and Chapter 12.2 (goodput vs availability). The compute and packaging vocabulary maps to Chapter 7.1, Chapter 7.6 and Chapter 7.7. The fabric vocabulary maps to Chapter 8.2 (scale-up), Chapter 8.4 (scale-out protocols), Chapter 8.5 (topology) and Chapter 8.6 (congestion control). The phase-gate timeline is the appendix view of the integrated master schedule in Chapter 2.1, the interconnection critical path in Chapter 3.2, and the commissioning program in Chapter 13.1. The scoping artifacts the timeline assumes are produced in Chapter 1.1 and detailed in Chapter 1.7.

Cite this chapter

Fehn, J. (2026). Glossary, Phase-Gate Timeline & Learning/Community Map (Chapter E). The Definitive Guide to AI Data Centers. https://aidatacenterguide.com/appendix-appendices-and-reference-data/e-glossary-phase-gate-timeline-and-learning-community-map (accessed 2026-10-25).

@misc{aidc-E,
  author       = {Fehn, Jacob},
  title        = {Glossary, Phase-Gate Timeline & Learning/Community Map (Chapter E)},
  howpublished = {The Definitive Guide to AI Data Centers},
  year         = {2026},
  url          = {https://aidatacenterguide.com/appendix-appendices-and-reference-data/e-glossary-phase-gate-timeline-and-learning-community-map},
  note         = {Accessed 2026-10-25}
}

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