The Definitive Guide toAI Data Centers
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Chapter 5.1

Thermal Fundamentals & the Density Wall

Cooling is selected from the named rack and facility envelope: rack kW is one input alongside liquid/residual heat split, component heat flux, airflow and inlet limits, TCS/FWS conditions, room rejection, climate, serviceability, redundancy, and the refresh tail.

POWER-BOUNDDENSITY-RAMP

What you'll decide here

  1. Which named current and roadmap rack profiles the facility must support, including their heat split and flux, airflow/inlet envelope, TCS/FWS interfaces, residual-room duty, and service/redundancy case—because those requirements set the hard-to-retrofit structure, distribution, and heat-rejection provisions.
  2. Which air, RDHx/AALC, hybrid, or direct-liquid candidates close the complete equipment-and-facility envelope, and at which stated air/water temperatures, flows, pressures, fan state, and heat-capture target each product capacity is valid.
  3. The junction-to-coolant thermal-resistance budget you are designing against — the chip vendor fixes Tjunction and TDP, leaving you only the coolant temperature and the resistance stack to spend, and that budget decides whether a cold plate can keep the silicon legal.
  4. The approach temperature and effectiveness you target at every heat exchanger in the chain, because each delta-T you spend narrows the free-cooling window and pushes the facility toward mechanical chilling.
  5. Whether the irreversible substrate (floor loading, facility water, pipe-rack and CDU space, electrical headroom) is sized for the density ramp, even where the reversible IT fit-out is matched to the current generation.
Cooling paths overlap. Qualify each against the named rack heat split and flux, airflow/inlet limits, water conditions, residual-room rejection, climate, service/redundancy case, and refresh tail before fixing the hall's distribution and structure.

Every accelerator is, thermodynamically, a space heater that happens to do arithmetic. A 1,200 W GPU converts essentially all of its electrical input into heat, and that heat must be removed continuously and within a few degrees of a fixed temperature limit or the silicon throttles, ages, or fails. This is the one constraint in the building that does not negotiate. You can oversubscribe a fabric, defer a redundancy tier, re-price a power contract — but you cannot argue with the second law. The heat leaves through the path you built for it, at the rate physics allows, or the machine slows down to match the path you actually have.

Part 5 builds on this thermal foundation. It starts with heat-flux first principles and the thermal-resistance stack-up from junction to coolant, then follows the 2020–2027 rack roadmap while testing conventional air, close-coupled air, RDHx/AALC, hybrid, and DLC against named equipment and facility envelopes. The thermal metricsapproach temperature, NTU/effectiveness, airflow and pressure, coolant delta-T, flow, and pressure drop—become the qualification vocabulary. Rack kW narrows the feasible set; heat split and flux, airflow/inlet limits, FWS/TCS or entering-water conditions, room rejection, climate, service/redundancy, and the refresh tail select the service.

Heat flux and the resistance stack-up

The governing quantity is not power but heat flux — power per unit area, W/cm². A 700 W H100 die spread over roughly 8 cm² runs near 85–90 W/cm²; a Blackwell-class package past 1 kW pushes toward and beyond 100 W/cm² at the hotspot. For scale, that flux rivals a nuclear-reactor fuel rod and exceeds a domestic cooktop element by an order of magnitude. Flux is what the cooling solution actually fights, because heat removal is fundamentally limited by how much surface area you can couple to a coolant and how steep a temperature gradient you can sustain across it.

The chip vendor hands you two fixed numbers and no others. Tjunction-max — the maximum allowable on-die temperature, typically ~90–105 °C for datacenter accelerators — is a hard reliability and functional limit; cross it and the part throttles, then degrades, then fails. TDP — the thermal design power you must remove — is set by the silicon and the workload. Everything between the junction and the coolant is your design space, and it is governed by a simple, unforgiving relation: the temperature rise from coolant to junction equals the heat removed times the thermal resistance of the path, ΔT = Q × Rθ. Fix Q (the TDP) and Tjunction-max, and the resistance you can afford collapses to a fixed budget. Spend it badly and the chip is illegal at any coolant temperature you can practically supply.

The resistance stack is a series chain — Tjunction to Tcase to the cooling medium — and like any series circuit, the largest resistor dominates. Walk it from the silicon outward:

The junction-to-coolant thermal-resistance stack
StageInterfaceWhat it isWhy it dominates or doesn't
Junction → caseRθ-JC (in-package)Silicon → TIM1 → integrated heat spreader / lidLargely fixed by the vendor's package; you cannot improve it from outside
Case → cold plateTIM2 / thermal interfaceLid → second thermal interface → cold-plate baseThe most abused link; a poor or pumped-out TIM2 silently adds 5–15 °C
Cold plate → coolantConvective resistanceMicrochannel / skived-fin base → flowing coolant filmSet by flow rate, channel geometry, and coolant; where DLC wins over air
Coolant → facilityLoop ΔT + CDU approachTechnology-cooling loop carries heat to the CDU heat exchangerCumulative; every approach temperature here narrows free-cooling headroom
Representative single-GPU values for a ~1 kW datacenter accelerator under single-phase direct-to-chip cold-plate cooling. Resistances are order-of-magnitude design references, not vendor specs; the series sum and the coolant temperature together set the junction temperature.

The reason air lost is visible in the third row. The convective resistance from a surface to a fluid scales with the fluid's heat-transfer coefficient and the wetted area. Water's volumetric heat capacity is roughly 3,500× that of air, and its convective coefficient at a cold-plate surface is one to two orders of magnitude higher than forced air over a finned heatsink. Air can be pushed harder — more CFM, taller fins, colder supply — but each lever has sharply diminishing returns and a parasitic-fan-power penalty that eventually exceeds the heat it removes. Liquid operates in a different regime rather than merely beating air: it shrinks the case-to-coolant resistor by enough that the same TDP fits inside the same junction budget at a far more relaxed coolant temperature. → the cold-plate engineering is in Chapter 5.4; in-chip microchannels that attack Rθ-JC itself are in Chapter 16.2.

Why air hit a wall

Rack cooling is selected across overlapping equipment and facility envelopes; no universal rack-kW value is a physics cliff. The cited source instead reports 30–40 kW as a typical RDHx range and more than 50 kW with active rear-door fans; those are door-reference conditions, while actual air and liquid-assisted systems close or fail at different duties according to rack airflow and inlet limits, system pressure, containment and recirculation, fan state, acoustics, design-day rejection, service access, and refresh profile. Any published rack, door, or cooling-unit capacity must therefore carry its stated air and water temperatures, flow, pressure, fan state, containment, and heat-capture conditions.

Three physical constraints explain why air becomes unattractive as heat flux and airflow demand rise. First, on a given system curve, fan power rises approximately with the cube of airflow: increasing CFM can impose a steep fan-energy penalty, and the result must be modeled at the actual pressure and fan-efficiency point. Second, air's low heat capacity forces large temperature rises and large volumes; the supply-to-return delta-T air can carry is small, and you run out of mass flow before you run out of fans. Third, acoustic and velocity limits cap how hard you can blow before noise, vibration, and bypass airflow make the hall unworkable and the cooling ineffective at the chip. These constraints make conventional room air unsuitable for the cited 132 kW rack, whose OEM record already assigns ~115 kW to liquid and ~17 kW to air. That product-specific heat split — not subtraction from a universal rack-kW ceiling — establishes its DLC requirement.

Where the supported equipment roadmap may require water at the rack, reserve the hard-to-retrofit structure, routes, isolation, CDU space, and rejection capacity early, even though air, RDHx, hybrid, and DLC envelopes overlap. An inherited air hall may or may not lack those provisions; inspect it rather than assuming. Adding missing liquid and structural interfaces later can run ~$2M/MW (cooling-only) to ~$5–6M/MW and up and still strand power or floor capacity. This is a named equipment-roadmap and facility-envelope decision, not a workload or rack-kW lookup. → retrofit paths are engineered in Chapter 5.10; air-system qualification is in Chapter 5.2.

The density curve, 2020–2027

The density wall would be an academic curiosity if accelerators had stayed put. Per-GPU thermal design power has climbed from the A100's ~300 W to the H100's 700 W to GB200's ~1.0–1.2 kW, with the standard Rubin (VR200) package projected near ~2.3 kW — an analyst estimate that raised the earlier ~1.8 kW figure, not an NVIDIA specification — and Rubin Ultra higher still, with no per-GPU figure published. Multiply by the GPUs packed into a rack and the rack-level curve is steeper still, because the scale-up domain grew at the same time, concentrating more silicon behind a single liquid manifold. Across cited reference designs, the transition from H100-class air-capable configurations to the GB200 NVL72's declared liquid/residual heat split narrowed the feasible set from qualified air or RDHx paths to a supported DLC-plus-residual-air architecture.

Rack density by GPU generation, and the cooling regime each forces
Generation (year)Per-GPU TDPPer-rack drawCooling regime forcedRelation to the air cliff
A100 / HGX (2020–22)~300–400 W~10–20 kWAir; raised floor + containmentComfortably under the wall
H100 / HGX (2023)~700 W~30–40 kWAir at the limit; RDHx optionalAt the wall; air still wins for many
GB200 NVL72 (2024–25)~1.0–1.2 kW~120–132 kWDirect-to-chip liquid mandatory~3× over the wall; no air path exists
GB300 NVL72 (2025)~1.4 kW class~135–142 kW nominal (~155 kW peak)DLC; residual air load on RDHxWell over; hybrid liquid+air per rack
Vera Rubin NVL72 (2026)~2.3 kW (analyst est.)~190–230 kWDLC + 800 VDC power pathFar over; warm-water loops to free-cool
Rubin Ultra Kyber (2027)not published~600 kWDLC mandatory; in-chip microfluidics on the roadmapAn order of magnitude over the wall
Per-rack figures are NVIDIA-class reference points; 2026–2027 entries are roadmap, not shipping (Rubin TDPs and Kyber rack power are pre-shipment estimates). The regime column is the consequence the density forces — it is not a choice once the density is fixed.

The rightmost column is the consequence. As density and heat flux rise, the equipment profile narrows the feasible set, but selection still depends on liquid heat fraction, airflow/inlet limits, water availability, TCS/FWS conditions, climate/rejection, residual room heat, serviceability, redundancy, and the future tail. The only decisions left are when you cross (which generation your facility targets) and whether the irreversible substrate is ready when you do. A hall scoped for 40 kW air-cooled racks cannot absorb a 132 kW NVL72 generation, let alone a 600 kW Kyber-class rack — not the floor, not the power chain, not the cooling plant. The expensive mistake of the 2026 era is designing to today's density and being surprised by the ramp.

30–40 kW typical RDHx; >50 kW with active fans; not a universal limit
SemiAnalysis/nVent cited RDHx range: 30–40 kW typical and >50 kW with active rear-door fans; verify the named door/rack and facility envelope
~3,500×
volumetric heat capacity of water vs air — the reason liquid operates in a different cooling regime
132 kW nominal TDP: 115 kW liquid + 17 kW air
NVIDIA GB200 NVL72 by HPE: 132 kW nominal rack TDP, with 115 kW liquid and 17 kW air heat-removal duties
45 °C maximum liquid inlet; 65 °C maximum liquid return (separate limits)
QCT GB200 NVL72 QoolRack reference maxima: 45 °C liquid inlet and 65 °C liquid return; separate limits, not a selected operating pair
~132–142 kW nominal; ~155 kW peak
per GB300 NVL72 rack (up to ~155 kW peak); CPUs/GPUs/NVSwitch liquid, optics/storage air
~600 kW
per Rubin Ultra Kyber rack (NVL144) on 800 VDC (roadmap, 2H2027)
~2.3 kW
Projected standard Rubin per-GPU maximum power, compared with an approximately 0.3 kW A100 baseline—a roughly sevenfold climb
~$5–6M/MW → greenfield parity
cost to retrofit an air-cooled hall across the cliff to AI liquid cooling; still strands capacity
~$2M/MW
cooling-only liquid retrofit, power-suitable hall — the ~80%-cheaper scope the full-conversion figure is often confused with
33% → 53% → ~60%
liquid-cooling penetration among AI chips — the installed-base adoption curve behind the density ladder
even in 2026 nearly half of AI chips still run on air — the two-speed market is real, and the liquid share is compounding fast

The cooling hierarchy and where each rung saturates

Map the density curve onto the available cooling technologies and you get a hierarchy — a ladder where each rung removes more heat at higher capital cost and integration complexity, and each rung saturates at a density that hands the load to the next. Choose the lowest rung that clears your peak density with margin, because every rung up costs money, water, and plumbing complexity you do not get back.

  • Air (containment + CRAH/in-row). Saturates ~40–50 kW/rack. Cheapest, simplest, no facility water at the rack. Still the right answer for storage, networking, enterprise 8-GPU HGX and RTX PRO nodes, and edge. Frontier inference is not on that list: it lands on the same NVL72-class DLC racks as training, so the rung follows the named rack profile, not the workload label. → Chapter 5.2.
  • Rear-door heat exchangers / air-assisted liquid. Bridges ~50–100 kW/rack. Captures heat at the rack exhaust with a liquid coil; the brownfield-friendly rung because it needs no chip-level plumbing and tolerates facilities without facility water. Saturates where the door coil can no longer extract a high enough fraction of the heat. → Chapter 5.3.
  • Direct-to-chip liquid (single-phase DLC). A mainstream 2026 path; one reported forecast is ~55%, but PMR's published category is broader cold-plate liquid cooling rather than measured single-phase-DTC deployment share. Cold plates on the GPUs/CPUs/switches, in-rack manifolds, dripless quick-disconnects, a CDU isolating the technology-cooling loop from facility water. Clears 100 kW to 200+ kW and scales to the Kyber generation with warm-water loops. → Chapter 5.4; CDU loop in Chapter 5.6.
  • Immersion (single- and two-phase). Best-in-class PUE, but niche: single-phase wins on serviceability and floor loading, two-phase stalled on the PFAS reckoning and insurability. → Chapter 5.5.
  • In-chip / direct-to-silicon microfluidics. The next rung, attacking the in-package Rθ-JC resistor itself with microchannels etched into or onto the die — the only lever that touches the dominant resistance the cold plate cannot reach. Roadmap, not yet default. → Chapter 16.2.
Deep dive: the chain of delta-Ts, approach temperature, and why warm water decides free cooling

Heat does not teleport from the junction to the sky; it walks down a staircase of temperature drops, and every step costs you. SemiAnalysis frames this as the Four Delta-Ts, and it is the right mental model for the entire facility. Start at the junction (~90 °C limit). Drop across the package and TIMs to the cold-plate coolant. Drop again across the loop as the coolant carries heat to the CDU. Drop a third time across the CDU heat exchanger from the technology-cooling loop to the facility-water loop. Drop a fourth time at heat rejection — the cooling tower, dry cooler, or chiller that finally hands the heat to ambient. The junction temperature is fixed; ambient is fixed by your climate and season; everything in between is a budget of degrees you allocate across four exchangers.

The lever at each exchanger is approach temperature — the gap between the two fluids leaving a heat exchanger that never fully equalize. A tighter approach means a more effective (and larger, costlier) exchanger but a warmer achievable supply on the cold side. Formally this is captured by effectiveness and the NTU (number of transfer units) method: effectiveness is the actual heat transferred divided by the thermodynamic maximum, and it rises with NTU, which rises with exchanger surface area and overall conductance. More area buys more effectiveness buys a tighter approach buys warmer facility water for the same junction temperature.

Why does warmer water matter so much? Because it is the difference between free cooling and mechanical chilling. If your facility-water loop can run warm — ASHRAE's W17 through W45-plus classes key cooling water by supply temperature — a dry cooler or tower can reject heat to ambient for most or all of the year, and a PUE near 1.1 is reachable. If your delta-T budget forces cold supply water, you burn compressor energy on chillers, drive PUE up, and shrink your siting envelope to cool climates. Every degree you waste on a sloppy TIM or an under-sized exchanger upstream is a degree you cannot spend on free cooling downstream. This is why the 30 °C-coolant roadmap exists, and why warm-water design is treated as a first-class objective rather than an afterthought. → facility loops and warm-water design in Chapter 5.7; heat rejection in Chapter 5.8; the metric definitions in Chapter 15.1.

Thermal metrics used in this part

Part 5 leans on a small, consistent vocabulary of thermal metrics. Pin them down here so the engineering chapters can use them without re-deriving:

  • Approach temperature — the residual gap between the two streams leaving a heat exchanger. Smaller approach, more effective and more expensive exchanger, warmer achievable cold-side supply. The single knob you tune at every exchanger in the chain.
  • Effectiveness (ε) and NTU — effectiveness is actual heat transfer over the thermodynamic maximum; NTU is the dimensionless measure of exchanger size (conductance × area over the minimum heat-capacity rate). The ε-NTU method is how you size CDU and facility heat exchangers without solving the full temperature field. Higher NTU asymptotes toward ε = 1 with diminishing returns.
  • Delta-T (ΔT) — the temperature rise a coolant carries across a load. A larger ΔT moves the same heat at lower flow (smaller pumps, smaller pipes), which is why warm-water, high-ΔT design is favored. The flow-rate rule of thumb — ~1.25–2.0 L/min per kW — falls directly out of the ΔT you choose.
  • Heat flux (W/cm²) — power per die area, the quantity the cold plate actually fights at the hotspot, distinct from total TDP.

The facility-efficiency metrics — PUE, WUE, ITUE, and TUE — sit one level up, scoring the whole plant rather than a single exchanger. PUE is total facility energy over IT energy; WUE is water consumed per IT energy; ITUE and TUE extend the accounting to capture fan and pump parasitics that liquid cooling reshuffles. These are defined canonically in Chapter 15.1 and used throughout Part 5 as the scorecard for the design choices this chapter sets up; we name them here only so the cross-references resolve.

This chapter sets the foundation the rest of Part 5 builds on. Air pushed to its honest limit is Chapter 5.2; the rear-door bridge is Chapter 5.3; direct-to-chip liquid — the 2026 default — is Chapter 5.4; immersion is Chapter 5.5; the CDU and secondary loop are Chapter 5.6; facility water and warm-water design are Chapter 5.7; heat rejection is Chapter 5.8; and retrofitting across the cliff is Chapter 5.10. The density-and-cooling fork that this chapter treats as physics is framed as a scoping decision in Chapter 1.1; in-chip microfluidics that attack the in-package resistance live on the roadmap in Chapter 16.2; and the efficiency metrics that score every cooling choice are defined in Chapter 15.1.
Cite this chapter
Fehn, J. (2026). Thermal Fundamentals & the Density Wall (Chapter 5.1). The Definitive Guide to AI Data Centers. https://aidatacenterguide.com/part-5-cooling-and-thermal-management/5-1-thermal-fundamentals-and-the-density-wall (accessed 2026-08-28).
@misc{aidc-5-1,
  author       = {Fehn, Jacob},
  title        = {Thermal Fundamentals & the Density Wall (Chapter 5.1)},
  howpublished = {The Definitive Guide to AI Data Centers},
  year         = {2026},
  url          = {https://aidatacenterguide.com/part-5-cooling-and-thermal-management/5-1-thermal-fundamentals-and-the-density-wall},
  note         = {Accessed 2026-08-28}
}
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