Advanced Packaging & the Integration Substrate

"How fast is this chip?" used to be answered at the transistor: a smaller node, more transistors, a faster clock. That era is functionally over for AI silicon. A single reticle field — the largest area a lithography scanner can pattern in one shot — is about 858 mm² (roughly 26 × 33 mm), and the largest useful monolithic die is already pressed against that limit. An H100-class GPU is essentially a full-reticle die. You cannot make the logic meaningfully bigger by printing it; you have hit the reticle wall. Everything that has happened to AI accelerator performance since is, at the physical level, a packaging story: how to stitch multiple reticle-sized fields together, how to bolt a dozen HBM stacks beside the logic, and how to wire it all with enough bandwidth that the assembled system behaves like one chip. The package is the integration substrate, and the firm that controls the largest, highest-yielding package controls how much compute the world can ship.

This chapter is the engineering of that substrate. We lay out the 2.5D/3D packaging taxonomy and why it is the most-cited binding constraint on AI compute through 2030; the CoWoS-S/R/L families and SoIC / hybrid bonding, and the reticle-stitching and per-package-area ceilings each imposes; the interposer fork (silicon vs RDL vs glass) and its reach/cost/yield triad; the way HBM-stack-count-per-package falls directly out of interposer area — the engineering driver behind the allocation view of Chapter 7.6; chiplet disaggregation and UCIe and the economics of every die-to-die crossing; and the thermal, warpage, and yield consequences of building packages the size of a coaster. Procurement and allocation of CoWoS capacity stay where they belong — in Chapter 7.6 and Chapter 2.3 — and we point there rather than re-litigate them. Here we own the physics.

The constraint moved upstream the same way power did in the facility. The industry assumed the gate on accelerator supply was wafer-out logic — how many GPUs a leading-edge fab could print. It is not. The gate is advanced packaging capacity, specifically TSMC's CoWoS lines, which through 2026 are fully booked across both the CoWoS-S and CoWoS-L families. Total 2026 CoWoS demand is estimated near 1 million wafers, against a capacity ramping toward roughly 110–130k wafers/month by year-end, up from ~13k/month at the end of 2023 (TrendForce; Silicon Analysts; TSMC reporting, 2026). A logic wafer that cannot be packaged is not an accelerator. That is why a chip company can have ample N3/N5 logic allocation and still ship late: the bottleneck is the CoWoS slot, and the CoWoS slot is set by interposer area and stack count, which is the engineering this chapter governs.

The tradeoff is sharp. Choosing a more aggressive package — more reticles stitched together, more HBM stacks — buys performance, but it consumes disproportionately more CoWoS capacity per accelerator (a 5.5×-reticle part eats far more interposer area, and yield risk, than a 2× part) and pushes the program onto the newest, least-mature, most-allocation-starved process. Choosing a conservative package preserves yield and supply but caps memory bandwidth and compute area. There is no free axis: the package is where the GOODPUT ambition of the silicon team collides with the DENSITY-RAMP reality of the packaging line.

Advanced packaging splits cleanly into two regimes, and the fork between them is the first decision an architecture team makes. 2.5D places multiple dies side-by-side on a shared horizontal carrier — an interposer — that routes thousands of fine wires between them. This is how logic meets HBM today: the GPU die and its HBM stacks sit beside each other on a silicon (or RDL, or glass) interposer, with HBM's wide thousand-plus-bit bus fanned out across that carrier. CoWoS is the canonical 2.5D flow. 3D stacks active dies vertically, face-to-face, bonded directly so that a die sits on top of another die rather than beside it. TSMC's SoIC and the hybrid-bonding processes underneath it are the 3D flow; AMD's MI300 stacks compute chiplets on base dies this way, and the HBM stack itself is a 3D structure internally.

The consequence of the fork is geometric. 2.5D buys you area — you spread components across a large flat carrier, and the limit is how large an interposer you can yield. 3D buys you proximity and density — wires between stacked dies are microns long instead of millimeters, slashing interconnect energy and latency, but you inherit a severe thermal problem (the die on top has to dump its heat through the die below) and a yield-multiplication problem (a bad die anywhere in the stack can scrap the whole assembly). Real 2026 accelerators are hybrids: a 2.5D interposer carrying 3D-stacked logic and 3D-stacked HBM. The package is two integration technologies at once.

The table is the central engineering fork of the chapter. CoWoS-S uses one big slab of TSV-bearing silicon as the interposer — the cleanest electrically, but a large silicon interposer is expensive and its own reticle-stitching limits cap how big it can get. CoWoS-R drops the silicon for an organic RDL carrier — cheaper and more warpage-tolerant, but with coarser routing and fewer stacks, a deliberate down-spec for cost-sensitive parts. CoWoS-L is the 2026 frontier: it abandons the single monolithic silicon interposer for an RDL carrier with small local silicon interconnect bridges embedded only where dense die-to-die routing is needed — letting the package span far more than a single reticle (~5.5× in volume now, with a ~9.5× node on the 2027 roadmap supporting 12 HBM5 stacks) while spending silicon only where it earns its cost. The consequence of choosing -L is that you inherit a new family of yield-loss mechanisms — bridge-to-RDL alignment, stitching seams, larger-package warpage — in exchange for the area no single silicon interposer can give you.

Where 2.5D spreads outward, SoIC (System-on-Integrated-Chips) stacks upward using hybrid bonding — a bumpless, copper-to-copper, dielectric-to-dielectric direct bond that eliminates the solder microbumps of older 3D stacking. The payoff is interconnect density: classic microbump pitch is ~40–50 µm; hybrid bonding takes the bond pitch into the single-digit-micron range and, on the roadmap, sub-micron. That is one-to-two orders of magnitude more vertical connections per unit area, which is what lets two dies behave electrically as if they were one — picojoule-per-bit interconnect, full-bandwidth die-to-die, latency measured in fractions of a clock. AMD's MI300-class parts stack compute chiplets on a base die this way; HBM itself is a hybrid-bonding story internally as stacks climb to 12-Hi and 16-Hi.

The 3D ceiling is thermal, and it is a hard one. When you put logic on top of logic, the upper die's heat must traverse the lower die to reach the cold plate, and power density at the bond interface can exceed what any external cooling can extract without throttling. This is why 3D-on-logic is selective — you stack the parts that benefit most from proximity (cache, certain compute tiles) and keep the hottest, highest-power logic where it can see the cold plate directly. The decision to go 3D is a decision to make the cooling problem of Part 5 harder in exchange for interconnect you cannot get any other way. The forward pointer is explicit: large-package hotspot and heat-flux behavior is engineered in Chapter 5.1 (the density wall) and removed by the cold plate in Chapter 5.4.

Underneath the CoWoS branding sits the real material decision: what is the carrier made of? Three answers, three reach/cost/yield triads. Silicon interposers route the finest lines and carry TSVs for power and signal straight through — best signal integrity, the obvious choice for HBM's wide bus — but a large silicon interposer is costly, is itself reticle-limited (you cannot pattern one bigger than a scanner field without stitching), and its CTE mismatch against the organic substrate drives warpage as it grows. RDL (organic redistribution-layer) carriers are far cheaper and more warpage-forgiving and can be made large, but route coarser and carry less bandwidth density — hence CoWoS-L's compromise of an RDL carrier with silicon bridges only where density is mandatory. Glass is the emerging third option: glass-core substrates and interposers promise the dimensional stability and flatness of silicon at lower cost and at panel scale, with excellent high-frequency loss characteristics — but the ecosystem is immature, with handling, via-formation, and crack-propagation risks still being industrialized through 2026.

This is the link that ties this chapter to the memory chapter, and it is worth stating as a near-identity: HBM stacks per package is a function of interposer area, not of how much HBM you can buy. Each HBM stack occupies a fixed footprint beside the logic die and must be reached by a thousand-plus-wire bus fanned across the interposer. Eight stacks fit on a ~3×-reticle silicon interposer; getting to 12 stacks requires the ~5.5×-reticle area that only CoWoS-L delivers in volume in 2026; 16+ stacks need the next reticle-multiple node still ramping. So when Chapter 7.6 describes HBM as the top-3 BOM line and the binding allocation gate, the engineering reason a given accelerator carries the stack count it does lives here: the package area the program chose set the stack count, which set the memory capacity and bandwidth, which set where it lands on the memory roadmap.

The decision consequence is that memory ambition and packaging ambition are one decision. A team that commits to a 12-stack, ~288 GB HBM4 accelerator (Rubin-class, ~2 TB/s/stack) has by that act committed to a 5.5×-reticle CoWoS-L package, its yield curve, and its slice of the scarcest packaging capacity on earth. You cannot buy your way to more bandwidth without buying your way to more interposer area, and interposer area is exactly the thing in shortest supply. The procurement reflex — "order more HBM" — is necessary but not sufficient; without the CoWoS slot to mount it on, the HBM is inventory, not bandwidth. That allocation logic is owned by Chapter 2.3; the engineering driver is owned here.

Once the reticle wall makes one big die impossible, the question becomes how to build a big system from small dies — and that is the chiplet decision. Disaggregation splits a would-be monolithic SoC into multiple dies ("chiplets") that are packaged together: compute tiles, I/O dies, cache dies, each potentially on a different process node tuned to its job. The upside is real and quantifiable. Yield improves super-linearly as die size shrinks — defect density punishes large dies brutally, so four small dies yield far better than one die of the same total area. You reuse a chiplet across many products. You put I/O on a cheap mature node and spend leading-edge wafers only on the logic that needs them. AMD productized this years ago; it is now the default architecture for the largest accelerators.

The cost of disaggregation is paid at every die-to-die crossing, and this is where UCIe (Universal Chiplet Interconnect Express) enters. A monolithic SoC routes between blocks for free, on-die. A chiplet system must serialize, drive across a physical die boundary, and deserialize — spending area on PHYs, power on the link (picojoules per bit that add up across terabytes per second), and latency on the crossing. UCIe standardizes that interface so chiplets from different vendors and nodes interoperate, with a 2.5D ("standard package") profile and a hybrid-bonded 3D ("advanced package") profile reaching >20 Tbps/mm of edge bandwidth density and, in 3D, areal densities into the hundreds of TB/s/mm². The strategic consequence of UCIe is an open chiplet market: a buyer can, in principle, assemble an accelerator from best-of-breed dies rather than one vendor's monolith — the packaging-era analog of the open-system disaggregation Part 8 describes for the network.

Large packages punish you three ways, and each is a downstream cost of the area you bought to defeat the reticle wall. Warpage is the first: a large silicon interposer on an organic substrate has a coefficient-of-thermal-expansion mismatch, and as the assembly heats and cools it bows. Past a certain span the bow threatens the solder joints to the board and the bond integrity across the package — which is a major reason CoWoS-L's RDL-plus-bridge construction exists (the organic carrier is more compliant) and why glass cores are attractive (dimensionally stable and flat). Warpage is not a yield footnote; it is a first-order limit on how large a package you can build at all.

Yield is the second, and large packages multiply it sharply. A 12-HBM, multi-reticle, stitched package is the product of many independent yields (each die, each HBM stack, each bond, each stitch seam), and a defect anywhere late in the flow scraps an assembly carrying enormous accumulated value (a dozen HBM stacks and multiple known-good logic dies). This is why known-good-die testing before assembly is non-negotiable and why the largest packages carry the largest scrap-cost exposure: you are gambling the most expensive components on the last and least-reversible step. Thermal is the third: a large, dense package concentrates hundreds of watts into a small footprint with internal hotspots over the 3D-stacked regions, producing heat fluxes that air cannot remove and that even direct-to-chip liquid must be engineered for. The package's heat-flux map is the boundary condition the cold plate inherits — the explicit hand-off to Chapter 5.1 and Chapter 5.4.

Walk the chain forward and the package sits at the center of it. The reticle-multiple you choose sets the interposer area; interposer area sets the HBM-stack count, which sets memory capacity and bandwidth (→ Chapter 7.6); the reticle-multiple also sets which CoWoS family and OSAT can build it, which sets yield and lead time (→ Chapter 2.3); the package's power and heat-flux map sets the cooling boundary condition (→ Chapter 5.1, Chapter 5.4); and the on-package power-delivery and di/dt behavior that a big, dense package demands is its own engineering problem (→ Chapter 7.12). The package is not a step in the flow; it is the substrate every other accelerator decision is mounted on. Get its reticle-multiple and family wrong and you have either an accelerator you cannot get capacity to build or one whose memory and compute ambition you under-shot — and unlike a board respin, a package family change is a multi-quarter, multi-million-dollar reset.