Custom ASICs & the Merchant-Silicon Disruption

The previous four chapters treated accelerators as products you select. Here silicon is something you can commission, and the first question is whether the workload is big enough, durable enough and stable enough to pay back a chip you must design, validate and manufacture before it earns a cent. The merchant-GPU model (buy NVIDIA, inherit CUDA and the allocation queue) is the default because someone else paid the fixed cost. A custom ASIC inverts that bargain. You absorb the non-recurring engineering (NRE) and the lead time up front, in exchange for a chip tuned to your workload at a potentially lower cost per token after program costs, with only the programmability you designed in. In the 2025–2026 era the trade became a funded alternative for the largest inference buyers, though each one still needs its own program case. Merchant-silicon design houses (Broadcom, Marvell) turned chip design into a service you can buy.

The economics come first: NRE, lead time, minimum volume and the breakeven against a merchant GPU. Next is the specialization-versus-programmability fork, which decides whether the bet survives an architecture shift. Last is the hybrid fleet, which mixes custom and merchant silicon. Custom does not mean fixed-function: TPU and Trainium are programmable accelerators, and how much flexibility a chip keeps is a separate design choice. A custom ASIC is the highest-leverage and least-reversible procurement decision in Part 7. Clear the volume, software and delivery gates and you can earn a lower cost per token. Miss them and you own a stranded mask set and a chip that lost to the next merchant generation before it shipped. The XPU programs themselves are in Chapter 7.4, and the merchant GPUs you are deciding against are in Chapter 7.2 and Chapter 7.3.

A custom ASIC has two cost components that a merchant GPU hides from you, because NVIDIA amortizes them across millions of units. NRE is the one-time cost to design, verify and tape out the chip. Per-unit recurring cost is wafer, memory (including HBM where the design uses it), packaging and test, drawn from the same supply chain the merchant GPU uses. The case for building rests on one inequality: does the matched useful-service cost advantage, multiplied by your committed volume, exceed the NRE plus software, integration, sustaining and delay cost? Below that threshold the program never pays back. Above it, every unit past breakeven is structural margin.

NRE is the number that disciplines the decision. At the leading edge the fixed cost of a new design has exploded: IBS estimated $590M to develop a mainstream 3 nm chip, versus $416M at 5 nm and $217M at 7 nm (Semiconductor Engineering, May 2021). The mask set is the smaller part. A leading-edge set passed $10M at 7 nm and heads toward ~$40M at 3 nm (SemiAnalysis, July 2022). Most of the cost is the verification, validation, IP licensing and physical-design labor that a leading-edge tape-out demands, and that labor is spent long before a shippable part exists. For a complete hyperscale accelerator program the reported figure is ~$500M for a single chip version, roughly doubling once the software and peripherals around it are built (Reuters, February 2025). A node-cost estimate or a mask-set price is therefore a floor, not a program budget. Budget chip design, software, package qualification, sustaining and a delay reserve as separate lines, as the worked case below does with the guide's own teaching numbers.

Then the lead time. From committed architecture to silicon in a rack, the development clock consumes the remaining commercial window. A tape-out alone costs tens of millions and typically takes about six months to return finished silicon, unless the buyer pays substantially more for expedited manufacturing (Reuters, February 2025). Design, qualification and rack integration come on either side of it. NVIDIA and AMD ship a new generation roughly annually, so a multi-year custom program races a moving target that may be a generation or two newer and more capable by the time the chip lands. Delay does more than slip revenue: it strands an otherwise excellent chip. Plan against the latest wafer, memory, package and system-release dates, and name who requalifies each alternative supplier. Chapter 2.1 builds the integrated schedule and Chapter 1.8 the discounted investment appraisal.

The table is a fixed-cost ladder. A merchant GPU carries no buyer-funded chip-design NRE and gives broad programmability. The vendor owns chip design while you keep utilization and resale risk, and you pay for all of it in the unit price and the allocation queue. Full in-house silicon gives maximum control and potentially lower recurring unit cost at proven volume, at the price of the deepest fixed cost and the longest clock. The co-design middle divides IP, yield, package test and sustaining duties between you and the partner in its statement of work. None of them disappears.

Co-design also comes in more than one form. Counterpoint Research's April 2026 example is Google's training-focused TPU 8t with MediaTek: Google designs the compute die and buys the HBM itself, while MediaTek supplies the I/O die. Counterpoint says this lets Google skip the HBM sourcing markup of Broadcom's turnkey model. Whichever form you pick, the statement of work should spell out who owns the design and IP, who absorbs yield loss, and who qualifies the package and carries the supply obligations.

A fourth route avoids a chip program altogether. You can buy specialized systems that someone else funded, such as NVIDIA's Groq 3 LPX racks, or hosted wafer-scale inference capacity from Cerebras. Compare their quoted service cost, software and integration work, and workload coverage against commissioning custom silicon. Chapter 7.1 and Chapter 7.2 cover the platforms, and Chapter 7.4 covers TPU access routes.

Fixed program cash is design + software + integration + service years × sustaining + delay reserve: $300M + $60M + $40M + 3 × $20M + $40M = $500M. The matched saving is merchant minus custom cost on the same useful-service basis, $50,000 − $35,000 = $15,000 per device over the 3-year window. At 40,000 devices that is $600M of saving against $500M of fixed cash, a $100M surplus. Volume break-even is fixed cash divided by saving per device: $500M ÷ $15,000 = 33,333⅓, so the program needs 33,334 devices. At 30,000 devices the saving is $450M and the program loses $50M.

A slip cuts the saving; the fixed cash is untouched. Saving is counted as service delivered at $5,000 per device-year, so a year's delay leaves two service years, and 40,000 × 2 × $5,000 = $400M. You still pay the sustaining team for the lost year and you draw down the delay reserve, so the $500M holds and the result is −$100M. A real slip usually costs more, because you also have to buy merchant capacity for the year you lost.

Take the base case forward and reject the lower-volume and slipped ones. A mask set cannot earn back design cash after the workload's window closes. Get a statement of work, committed service volume and software ownership in hand before sending these cash flows to the discounted appraisal in Chapter 1.8. The split into design, software, integration and sustaining work follows Synopsys's silicon-success guidance, which supplies none of the amounts.

Custom silicon went from a Google-only curiosity to an industry-wide wave because you no longer need Google's silicon organization to do it. Broadcom and Marvell turned ASIC design into a service. They bring hardened IP (SerDes, the highest-bandwidth interconnect and PCIe and scale-up blocks, memory controllers, packaging methodology) and a proven path through TSMC's advanced nodes and CoWoS, and the customer brings the compute architecture and the workload. That is the merchant-silicon disruption. Hyperscalers building chips is old news; buying a custom chip is now a procurement line item rather than a decade-long capability build.

The shift is real but still a minority of systems. In April 2026 TrendForce trimmed its forecast for ASIC-based AI servers to around 27% of 2026 unit shipments, from nearly 28%, citing validation and tuning time at Meta and AWS. GPU-based systems remain the majority. Among design partners, Counterpoint Research's January 2026 forecast puts Broadcom near 60% of 2027 compute-ASIC shipments for AI servers and Marvell near 8%, even as Marvell's shipment volume doubles.

Broadcom leads, and it anchors Google's TPU line (it also ships TPUs to Anthropic), Meta's MTIA and OpenAI's first accelerator, Jalapeño. It says it has six XPU customers. In fiscal Q3 2026 (reported September 2026) its AI semiconductor revenue, accelerators and AI networking together, was $16.7B, up 221% year over year, with XPUs about 73% of it. It guided $21.7B of AI semiconductor revenue for the next quarter.

On the same call (2 September 2026) Broadcom said it had begun production shipments of Google's TPU 8i and expects Anthropic to deploy about 5 GW of TPU 8i in 2027, becoming its largest XPU customer. It also described OpenAI's plan for 1.3 GW of its custom accelerator in 2027. For 2028 it claims line of sight to more than 5 GW for OpenAI and an incremental 10 GW for Anthropic. Its Meta figure is cumulative: three MTIA generations delivered by the end of 2027, and what Broadcom calls line of sight to roughly 3 GW of them deployed through 2028. These are Broadcom's forward statements, not installed capacity, but they put the leading programs far beyond the volume threshold of the worked case above.

On October 6, 2026 Marvell management said it expects about $12B of total revenue in fiscal 2027 and aims for more than $12B of custom revenue (XPUs and XPU-attach products) in fiscal 2029. In July 2026 Marvell also signed an agreement with Google covering custom products that attach to the TPU ecosystem.

The supplier field is wider than two companies. Marvell, MediaTek and Alchip are other design-partner options. For a strategist, the custom-silicon path is real and serviceable. A generation built on TSMC, CoWoS and HBM shares those capacity pools with the NVIDIA GPUs you were trying to escape. Building custom does not exit the supply chain; it re-enters from a different door. The upstream allocation gates are Chapter 7.6 (HBM) and Chapter 7.7 (packaging), and procurement strategy is Chapter 2.3.

A custom ASIC gets its cost advantage from specialization, and its central risk depends on how much programmability it keeps. A merchant GPU is a general matrix engine that runs whatever the compiler emits. A custom accelerator can also be compiler-programmable, as TPU and Trainium are. A fixed-function inference ASIC instead bakes in assumptions about precision, attention pattern, memory hierarchy and collective shape, and spends the transistors it saved on flexibility to do your workload faster and cooler. That is why it wins on tokens/$/W, and why it is exposed when the workload moves.

One direction is fixed-function efficiency: harden the datapath to the model architecture you serve today (a specific MoE shape, a specific KV-cache layout, FP8/FP4 microscaling) and you capture the full cost-per-token advantage, for that architecture. The other is reprogrammable flexibility: keep enough generality that a new attention mechanism, a new precision format or a shift from dense to wide-MoE does not strand the silicon, and give back some of the efficiency that justified building at all. The cost of choosing wrong is asymmetric. A model change after tape-out can be handled in software when the existing instruction set, memory and interconnect support it at acceptable throughput and latency. A respin is needed when the chip lacks a capability the new model requires, and a respin can add tens of millions and multiple quarters (guide scenario).

Google's first TPU shows the price of a missing capability. It ran integer arithmetic only. Early in its design Google's application teams accepted a 1% quality loss from quantization; by the time the chip was deployed in 2015 they no longer did, and restoring quality with integers could take months of extra work. The workload also moved under it: BERT appeared in 2018 and was 28% of Google's inference work by 2020, and production models grew about 1.5x a year in memory and compute. Google's lesson was that an inference chip may offer quantization but should not require it, and that it needs programmability and headroom to track model progress (Jouppi et al., ISCA 2021). Its successors kept a programmable matrix core and added floating point, and the line carried through the shift to transformers.

At the scale where a custom program pays for itself, an all-custom fleet and an all-merchant fleet fail in opposite ways, and a mix can hedge both. An all-merchant fleet leaves the cost-per-token advantage on the table for workloads that could capture it. An all-custom fleet is one architecture shift away from a stranded write-down. A hybrid fleet routes each workload to the silicon whose stability and volume it matches.

The partition follows from the prior sections, and owning a chip is a separate question from how programmable it is. Frozen, high-volume production inference, the stable serving tier, is the first candidate for custom silicon. A 30–40% price-performance advantage of the kind AWS claims for Trainium turns into roughly 23–29% lower cost at equal output. The moving frontier (pre-training, RL, research, and any model whose architecture is still in flux) needs the broadest operator coverage. Merchant GPUs are the default there. Programmable custom accelerators such as TPUs and Trainium can train too, if their operator coverage, useful throughput, latency and software cost hold up on your models. The bridge cases, new models still ramping toward stable volume or workloads with uncertain longevity, stay on the more flexible platform until they prove durable enough to migrate. The ratio between tiers is itself the hedge. Tune it to how much of your demand is frozen and huge versus still moving, and re-decide it each generation rather than committing once.

For procurement, build-versus-buy is neither binary nor permanent. It is a continuous allocation problem. Migrate a workload to custom silicon only once it crosses the volume-and-stability threshold, keep the merchant GPU as both default and escape hatch, and treat the custom fraction of the fleet as a position you re-balance, not a one-way door. Fleet composition and heterogeneous procurement are in Chapter 7.11, and the refresh and depreciation cadence that governs when custom silicon is retired is in Chapter 14.9.