CoWoS · Chip-on-Wafer-on-Substrate
TSMC's 2.5D packaging that joins logic die and HBM stacks on a silicon interposer; its wafer capacity gates AI supply.
TSMC advanced-packaging process integrating compute and memory on an interposer; an upstream supply chokepoint.
Also written as: Chip-on-Wafer-on-Substrate
Current numbers
~336 Btransistors per Rubin GPU (dual-die CoWoS-L), 1.6x Blackwell's ~208 B
~120–140k wafers/monthTSMC CoWoS capacity in 2026, from ~75–80k wafers/month; +50–60k at OSAT partners (TrendForce, June 2026)
5.5× (volume, 2026) → 9.5× (2027) → 14× (2028)CoWoS-L reticle multiple: 5.5× in volume (2026), 9.5× and 14× targeted; not the 100×100 mm substrate size.