Network Silicon: Switch ASICs, NICs & DPUs

The fabric chapters on either side of this one cover scale-up (Chapter 8.2), scale-out protocols (Chapter 8.4) and topology (Chapter 8.5). All of them assume a set of silicon building blocks and reason about how to wire them together. This chapter is about the blocks: the three classes of programmable silicon an AI network is built from. The switch ASIC moves packets between ports. The NIC (and its beefed-up cousin, the SuperNIC) connects a server's accelerators to the wire and runs the RDMA transport. The DPU/IPU is a NIC with a CPU complex bolted on, sitting in the data path to offload storage, security and virtualization from the host. Choose the silicon well and the fabric design that follows is a set of well-posed wiring problems. Under-spec the SerDes, mismatch the usable buffer to the admitted burst, or buy a DPU you have no offload for, and you have built in a ceiling that no topology cleverness can lift.

These decisions come early and stay sticky. The switch ASIC family fixes your radix and your lock-in before a single cable is run. Its SerDes generation fixes, for the next several years, how many ports you get, how far copper reaches and when optics become mandatory. The DPU decision (whether to deploy one at all, and what to run on it) is a per-server line item across thousands of servers, and it pays back only if you move work onto it.

Marketing leads with “102.4 Tbps switch” or “800G NIC,” but the spec that gates the design is the complete port definition: MAC service rate, electrical lanes, coded signaling, FEC, cage arrangement and supported breakout. The lane still sets how many interfaces fit and how far the electrical route reaches before optics add power and cost. A vendor’s 224 Gb/s-class SerDes label and 200 Gb/s-per-lane Ethernet service are not consecutive generations, and multiplying the electrical ceiling by lane count does not give useful Ethernet throughput. Cisco’s G300 data sheet dated 2026-02-10 lists the electrical and MAC specifications separately. IEEE P802.3dj is still a draft project, so specify the interface document and FEC mode rather than calling a product port a ratified application.

Why does the lane matter alongside the aggregate? Broadcom’s Tomahawk 6 launch shows the slicing. Its 2025 announced 102.4 Tb/s MAC capacity supports 64 × 1.6T, 128 × 800G or 256 × 400G logical-port modes, while a purchased box implements only some of those arrangements. An optical module can also gearbox between different electrical and optical lane counts. Count ASIC-to-module lanes, optical transmit lanes and active fibers separately, because none of them is the number of faceplate cages. Read the supported modes from the switch and module releases together, then confirm the host/NIC path reaches them. The copper cliff is a route constraint, not a universal meter count: lower-rate electrical lanes can improve a validated copper route while using more lanes per port, so “newer SerDes” alone does not settle reach or power. Chapter 8.9 covers the physical-layer consequences, and Chapter 8.4 covers the transport operations the endpoints implement.

Switch silicon differs on buffer organization, forwarding features and support boundary as well as aggregate rate. Broadcom Tomahawk and Jericho, Cisco Silicon One G300, and NVIDIA Spectrum and Quantum all belong in the same comparison. So does Marvell’s Teralynx T100, another merchant 102.4 Tb/s Ethernet ASIC: 3 nm, radix up to 512, BGA, co-packaged-copper or CPO packages, and SAI/SONiC support. Marvell said sampling would begin in Q2 2026 (1 June 2026 release), and the table below has no column for it, so ask its system partners for the same rows. Buffering philosophy decides where bursts wait, and the business model decides who controls support and replacements. Keep the ASIC supplier, the system supplier and the NOS separate: a chip’s SDK feature does not prove that the software release you buy exposes it. Freeze one supported combination of SKU, firmware, driver, NOS, transceiver and collective library, then ask which row of the table below stops that combination from carrying the topology. A missing queue-allocation or telemetry line is a gap in what the supplier has committed to, even when every headline bandwidth number passes.

Broadcom Tomahawk is the merchant high-radix line. It favors on-chip shared buffering and endpoint-controlled traffic over storing prolonged overload in external memory. Broadcom’s 2026-03-12 release says the 102.4 Tb/s Tomahawk 6 family is shipping in production volume. That follows the initial launch and does not show volume availability for every package or optical variant. PFC/ECN and endpoint admission still have to limit bursts before the shared queues fill. Ask for the actual port map and the queue, load-balancing and counter support of the NOS you will run before turning chip radix into leaf capacity. Its successor is under way: on its 2026-09-02 earnings call Broadcom said it had taped out Tomahawk 7, a 200 Tb/s switch, and gave no ship date or lane rate. There are two ways to reach that capacity. One keeps Tomahawk 6’s 512 lanes and runs each at 400G, a rate whose IEEE standard work has barely started (Chapter 8.9). The other doubles the number of 200G lanes. On the 400G path an eight-lane port becomes 3.2T, so allow for those ports in cage pitch and fiber plant at the next refresh.

Tomahawk 6, Spectrum-6 and Quantum-X now also come in co-packaged-optics (CPO) versions. On 2026-05-31 NVIDIA said its Spectrum-6-based Spectrum-X Ethernet Photonics was in production. Its InfiniBand sibling, Quantum-X Photonics (the Q3450-LD, 144×800G, liquid-cooled), is in production at Lambda, which said in March 2026 that a GB300 NVL72 cluster of more than 10,000 GPUs runs on it. Partners showed systems built on Broadcom’s 102.4 Tb/s TH6-Davisson (Celestica, Delta and Micas) at OCP in October 2026, and Broadcom gave no availability date. One of them, Micas, plans to start producing its Davisson switch in Q1 2027. Buying CPO changes the operating model more than the speed. Fiber connectors and field-replaceable external laser modules take the place of the transceiver cage map. You lose the choice of optics vendor, and an optical-engine fault, unlike a laser-module fault, means a board or switch repair rather than a module swap. Cooling follows the system design, not the packaging: NVIDIA’s Photonics switches are liquid-cooled, while Broadcom’s 51.2 Tb/s Bailly platform (Tomahawk 5, March 2024) is air-cooled. NVIDIA’s claim of roughly 5x better optics power efficiency is a vendor figure. Chapter 8.9 and Chapter 8.10 cover the physics and the serviceability evidence.

Broadcom Jericho is the merchant deep-buffer, VOQ line: routing-class silicon that spends external memory on bursts too large for an on-chip queue budget. Broadcom’s August 2025 Jericho4 announcement advertises a 51.2 Tb/s family aggregate and HBM-backed packet buffering. Those resources buy time for a bounded mismatch between arrival and service, not more sustained capacity at the destination link. Compare packet-routing mode with scheduled-fabric mode, including fabric elements, the admission protocol, power and the backlog tail. Longer routes enlarge the feedback budget, but even a deep buffer eventually fills under sustained overload. Chapter 8.8 covers admitting cross-site traffic against the protected path.

NVIDIA Quantum and Spectrum provide InfiniBand and Ethernet system paths. Quantum-X800 offers 800G/port InfiniBand with SHARPv4 in-network reduction (14.4 TFLOPS of in-network compute, nine times the prior generation; NVIDIA, March 2024; mechanics in Chapter 8.6). On the Ethernet side, Spectrum-X pairs the switch with ConnectX NICs or BlueField DPUs, so one supplier stands behind switch, NIC and DPU together. Their collective offload and endpoint/switch features have to work in the exact software combination you buy. Cisco G300 is another current Ethernet candidate on the same axes, and Cisco reports the first G300 systems shipping (2026-10-12). Cisco also plans a 51.2 Tb/s, 200G-SerDes G302 for top-of-rack before the end of 2026 (forecast). A controlled comparison on your own workload can justify an integrated premium. The economic question is whether one support boundary saves enough integration and recovery effort to outweigh losing interchangeable components. Chapter 7.1 develops the merchant-versus-captive business model.

Tomahawk versus Jericho is the cleanest hardware fork in networking, and it has no free lunch. It turns on one question: where do you store a packet that arrives faster than its egress port can drain? Two silicon philosophies answer it differently.

Shallow shared-buffer ASICs (Tomahawk-class) keep a small, fast pool of on-chip SRAM shared across all ports. The bet is that short reach, a non-blocking topology and good endpoint congestion control (PFC/ECN/DCQCN, adaptive routing, packet spray: the machinery of Chapter 8.6) absorb bursts at the source, so the switch never needs to hold much. The payoff is the lowest latency, the highest radix and the lowest power per bit. The risk is that a real incast burst larger than the buffer forces you to drop (lossy) or assert backpressure (PFC), and PFC at scale brings head-of-line blocking and deadlock risk. Shallow buffering only works if the congestion-control loop is fast enough to keep the buffer from filling.

Deep-buffer VOQ ASICs (Jericho-class) attach large off-chip memory (HBM on Jericho4) and organize it as virtual output queues: a separate logical queue per egress destination, so a congested port cannot head-of-line-block traffic bound elsewhere. The payoff is absorbing enormous bursts and running lossless over long reach: a larger burst budget for RoCE over long DCI routes, as long as admission and feedback keep arriving bytes within it. Depth alone cannot prevent drops. The cost is real: added latency (a packet may sit in deep buffer), higher power and die area (HBM is not free) and higher $/port. You do not want deep buffers on a short-reach leaf, where they add latency you never needed. You do want them at the fabric edge that crosses buildings.

Work each line before choosing the leaf. The MAC total is 64×800 Gb/s=51.2 Tb/s per direction; downstream and upstream each carry 32×800=25.6 Tb/s. The cage map uses 64×4=256 electrical lanes, while the optical map has 64×8=512 transmit lanes and 64×16=1,024 active fibers. These counts are distinct. A 102.4 Tb/s ASIC can have enough aggregate capacity without the box you buy exposing these cages or modes. A 2×400GbE NIC such as ConnectX-8 fails the single-800GbE host line even though its aggregate is 800 Gb/s. On a ConnectX-8 fleet that is the cue to build two 400G planes (Chapter 8.5), not to reject the NIC.

The required usable queue allocation is 64×0.60=38.4 MB, inside the assumed 40 MB pool, but candidate A’s per-port cap of 0.512 MB fails. Reject that configuration before comparing throughput. The flip point is a documented and tested per-port allocation of at least 0.60 MB while all 64 required queues are active and the other pool reservations still fit. At that threshold the arithmetic works, and the purchase waits until test data confirms the cage map, host payload, telemetry and concurrent-buffer behavior. The G300 data sheet and SN6000 manual show why advertised chip features and system allocations are separate things. Chapter 13.7 covers acceptance of the installed combination.

The NIC is where the network meets the accelerator, and in AI fabrics it does far more than push frames. Its defining feature is RDMA (remote direct memory access). RDMA lets a GPU on one node read or write registered GPU memory on another without host data copies, provided registration, PCIe/IOMMU topology and software support the path (the CPUs still handle setup and control). It is the foundation that makes collective communication tolerable at scale. Two transports carry RDMA: native InfiniBand (NVIDIA ConnectX in IB mode) and RoCEv2 (RDMA over Converged Ethernet), which runs the same verbs over a routable Ethernet/UDP underlay. The NIC implements the transport in hardware. How well it handles congestion, retransmission and packet reordering is part of why one fabric advances the job while another wastes bisection capacity on retries or idle barrier wait, so measure the service rate and completion tail of your own job.

Through the Blackwell generation, one supported back-end reference pattern is one NIC attachment per GPU: an 8-GPU server carries 8×400G or 8×800G back-end ports (3.2–6.4 Tb/s per node), plus a separate, smaller NIC for the front-end/storage/management plane. The term SuperNIC denotes the AI-optimized variant: full transport offload, hardware support for the adaptive routing, packet spray and out-of-order reassembly that Ultra Ethernet and Spectrum-X require, and line-rate congestion handling. ConnectX-8 carries the Blackwell (B300) 800 Gb/s generation, with a port-structure subtlety that shapes fabric design. Its single 800 Gb/s physical port runs Ethernet as 2×400GbE (a single 800GbE link is unsupported; the same port does carry 800 Gb/s XDR InfiniBand). That is why the B300-generation reference design wires each GPU into two independent 400GbE planes, and B300 also supports four 200G planes (NVIDIA, 2025–26; see the planes pattern in Chapter 8.5).

The Rubin platform doubles per-GPU scale-out bandwidth to 1.6 Tb/s, delivered as two 800 Gb/s ConnectX-9 SuperNICs per GPU, eight per four-GPU compute tray. The 800 Gb/s C9180-class parts are the first in the family with single-port 800GbE, and a 400 Gb/s variant also exists (NVIDIA, 2026). On Vera Rubin, NVIDIA’s Spectrum-X Multiplane profile runs each 800G ConnectX-9 as 4×200G, for eight 200G planes per GPU (Chapter 8.5), so confirm which port profile you are buying before you size the fabric as single-port 800GbE. The ConnectX-8 and ConnectX-9 pair teaches a general rule: read a NIC’s supported link speeds alongside its aggregate, because the two differ across the whole 2026 field. The field is also no longer single-vendor. AMD’s Pensando Pollara 400 (announced October 2024 as the industry’s first UEC-ready AI NIC, generally available April 2025) and 800G Vulcano, and Broadcom’s Thor 2 and 800G Thor Ultra (full UEC feature compliance, per Broadcom), are endpoint candidates that compete with NVIDIA’s supported stack when their driver, transport and collective combination checks out in your tests. The table below maps them.

Ask the vendor which multipath transports the NIC runs today and how it will pick up the next one. Four now compete: MRC; UET, whose specification reached version 1.1 on 2026-10-12; Meta’s MetaRoCE, for which Meta announced open-source implementations at OCP on 2026-10-12 (the first ran on AMD Pensando NICs); and Google’s Falcon, open through OCP since 2023, which NVIDIA and Google plan to support on future ConnectX-10 SuperNICs. Chapter 8.4 covers the transports. A NIC that runs its transport in a programmable pipeline can take a new transport or spec revision as a firmware update. A NIC that fixes the transport in silicon may have to wait for its next generation. Put the vendor’s commitment to named spec revisions in the purchase contract.

Packet spray re-introduces vendor coupling at the endpoint. Spraying packets across all paths only works if the receiving NIC can reassemble out-of-order delivery in hardware, so the switch and NIC must agree. That makes Spectrum-X and UEC switch+NIC systems, not just switches. The transport semantics that ride on top (lossless vs lossy, in-order vs out-of-order) are the subject of Chapter 8.4.

A DPU (data processing unit; Intel's term is IPU, infrastructure processing unit) is a NIC with a programmable CPU complex, memory and accelerators added, sitting in the data path between the host and the wire. The canonical examples are NVIDIA BlueField, AMD Pensando, Intel IPU and the cloud-captive designs (AWS Nitro, Google's IPU work). The premise is infrastructure offload: move the storage initiator, the encryption, the virtual-network overlay and the security policy plane off the host x86 and onto the DPU. That frees host cores for the paying workload and creates an isolation boundary the tenant cannot see past.

The 2026 flagship sets the scale of the bet. The first BlueField-4 DPU pairs a 64-core Grace CPU (Arm Neoverse V2; ~6× the compute of BlueField-3 per NVIDIA; 64 billion transistors per HPCwire) with ConnectX-9 networking at 800 Gb/s, 128 GB of LPDDR5, a PCIe Gen6 host interface and an on-board SSD. NVIDIA’s 2025 schedule put it in early availability with the Vera Rubin platforms in 2026 (NVIDIA / HPCwire, 2025). NVIDIA had published no shipping date for the standalone card as of October 2026, so ask the supplier when it will deliver. A second, storage-optimized BlueField-4 processor pairs a Vera CPU with ConnectX-9 in NVIDIA’s STX architecture (GTC, March 2026); no STX partner platform had been reported shipping by October 2026 (Chapter 9.3). Either version is a server-class computer on a NIC, which is why the DPU is a decision rather than a default. You are adding a second CPU, a second operating system and a second control plane to every server, and it pays back only if you run infrastructure functions on it.

Three offload domains justify a DPU, and each is treated in depth elsewhere in the guide:

• Storage. The DPU acts as an NVMe-oF initiator and runs the GPUDirect Storage data path. It presents remote flash into GPU memory through the supported storage path and bypasses host CPU data copies on a supported direct path, while the CPU keeps setup and control. Remote latency and failure behavior stay in the budget. In the BlueField-4 generation the DPU can also terminate an Ethernet-attached KV-cache/context-memory tier for inference. Chapter 9.3 builds out the storage data path.
• Security and isolation. The DPU enforces the tenant VPC overlay, line-rate encryption over RDMA and microsegmentation policy in hardware the tenant root cannot reach. That is the hard isolation boundary for multi-tenant GPU clouds, and the substance of Chapter 11.6 and Chapter 11.7.
• Virtualization & the overlay. The DPU runs the VXLAN/VPC encapsulation and the software-defined network, so the host hypervisor (or bare-metal stack) is relieved of network virtualization. Top-tier neoclouds standardize on this model for bare-metal-with-VPC.

The recovered host budget is 16−6=10 cores, and the six remaining infrastructure cores pass the 12-core service limit. Multiply ten by the assumed value per core, subtract the installed price, then subtract 0.060 kW×3×8,760 hours×the assumed electricity price. What remains is the allowance for added lifecycle and support cost: about $840 per server over three years, rounded after the arithmetic. Choose the DPU only if the recovered-core test passes and incremental support stays below that allowance. Otherwise keep the host/NIC path or change the offload.

The flip is concrete: support below the unrounded allowance preserves this economic case, and a larger support bill reverses it. An isolation boundary that must survive tenant compromise can still require independent enforcement, but that is a separate requirement, not a financial saving to invent. Get the actual core measurement and support price before release. The GPUDirect Storage design guide describes the data-path mechanism; Chapter 1.8 owns the economic method and Chapter 11.6 owns isolation acceptance.

For the same hypothetical leaf, total switch heat is 800 W base electronics + 200 W fans/control + 64×16 W modules=about 2.0 kW. Four switches contribute about 8.1 kW, so the assumed 2.1 kW switch and 9.0 kW rack allowances both pass. These are switch-end modules only; the far-end modules belong to their host or neighboring-switch location. Cold spares add no operating heat, and a supplier total that already includes modules must not get them twice. Get the fully populated input-power curve, the cooling-fluid or airflow range, the fan failure mode and the inlet limit. Send the location-specific heat to Chapter 5.1 and the equipment qualification to Chapter 5.7. A bare ASIC power number cannot tell you whether the rack cooling works.

The three ASIC families resolve into one strategic choice: buy the network as a co-designed system from one vendor, or assemble it from merchant silicon. NVIDIA's pitch is that the switch (Quantum/Spectrum), the NIC (ConnectX) and the DPU (BlueField) are designed together, so features like SHARP, packet spray with hardware reassembly and line-rate encryption work end to end out of the box. NVIDIA reports roughly 95% data throughput for its Spectrum-X fabric at xAI’s Colossus (October 2024; Chapter 8.4 weighs the figure), but the combination you buy still needs its own workload and recovery test. The catch is that the system's value depends on owning both ends. Mix in a third-party NIC and the co-designed features degrade or disappear.

The merchant counter-case is Broadcom (Tomahawk for radix, Jericho for depth) plus a SuperNIC of your choosing plus an open NOS (SONiC, FBOSS). The open NOS does not tie you to one ASIC vendor: Meta and NVIDIA announced Spectrum integration into FBOSS in October 2025, and Meta plans Spectrum-6 switches under FBOSS in its N-IceCube design (reported 2026-10-12). That makes the NOS decision separable from the ASIC decision, through per-ASIC integration. The merchant path gives you a multi-vendor supply chain, no single-vendor margin capture and the freedom to mix optics and cables. The cost is doing the integration yourself and accepting that the most aggressive co-designed features (SHARP-equivalent in-network reduction) are not yet at parity. Choose the merchant Ethernet/RoCE path when a second qualified switch/NIC/NOS combination buys a real price or supply option. Reserve the integrated premium for jobs whose supported reduction, routing or recovery features save enough completion time and operating cost to pay for it. Chapter 7.1 develops the business-model and margin framing of merchant versus captive silicon.

The recurring silicon mis-selections all come from optimizing one number in isolation instead of reading the gating spec and its downstream cost:

• Buying the aggregate Tbps and ignoring the SerDes generation. A switch bought one SerDes generation behind spends twice the electrical lanes on each port at your speed, so the same aggregate bandwidth arrives as more cages, more front-panel area and a narrower set of supported port modes and breakouts. Copper runs the other way: a lower per-lane rate reaches further on copper, which is why Broadcom offers Tomahawk 6 as 512×200G and as 1,024×100G. Compare aggregate capacity, lane count, supported port modes, cage count and qualified reach as five separate axes. Read the lane, not the headline.
• Deep buffers everywhere. Putting deep-buffer routing silicon on short-reach leaf switches where a shallow-buffer high-radix ASIC belongs means paying latency, power and $/port for burst absorption the tier never needs. Match usable buffer to the admitted burst and feedback delay.
• A DPU with nothing to offload. Deploying BlueField-class silicon across a single-tenant cluster with no isolation requirement and no storage-offload plan buys a per-server capex line and a second control plane for a feature set you never enable.
• Mixing a third-party NIC into a co-designed fabric. Buying a Spectrum-X or SHARP-capable switch for its integrated features, then pairing it with a generic NIC that cannot do hardware reassembly or in-network reduction, means paying the captive premium and getting the merchant feature set.

Choose the ASIC, NIC and NOS as the combination that passes every required line, including the populated-switch thermal limit and the feature you keep after substitution. A missing buffer or operation line is grounds to change the configuration or hold the order. Accepting a bigger chip headline instead buys a ceiling that the real ports, software or cooling cannot reach.