On-Package Power Delivery & Power Integrity

Everything upstream of the accelerator package exists to deliver clean voltage to its pins: the substation, the AC distribution or (in the 800 VDC racks now coming) the DC spine, then the power shelf and busbar. The accelerator does not run on the 48V it receives there. Its core rail sits around 0.6–0.9V, so at the power of a 2026-class GPU the steady-state core current runs to the thousands of amps. Vicor calls peaks of up to 2,000A typical today. The newest parts at full power go beyond that. NVIDIA publishes no per-GPU Rubin power. SemiAnalysis estimates about 1.8 kW at Max Q and 2.3 kW at Max P, and Pegatron rates its Rubin server at 2.3 kW TDP support per GPU. On a 0.75–0.80V core, and assuming 80–85% of that power sits on the core rails, a package carries roughly 1,800–2,000A at 1.8 kW and 2,300–2,600A at 2.3 kW, split across its two compute dies. On-package power delivery converts 48V to sub-1V at multi-kiloamp current, as close to the die as manufacturing allows, and holds the rail flat through load steps of hundreds of amps in nanoseconds. It is the least visible, highest-stakes meter in the power chain.

The action here plays out at the millimeter and microsecond scale. The path runs from board 48V down to core (multiphase VRMs and smart power stages), through the fork between lateral and vertical power delivery and the silicon-level move to backside power (BSPDN), to the PDN impedance target and the decoupling hierarchy that meets it, and finally to the load-line, Vdroop, and the di/dt event. That last item shares its cause with the facility transient: the same synchronized workload, summed across 72 GPUs at the iteration timescale, becomes the load swing the BBU/BESS spine must absorb. Guess wrong at any layer and you either strand silicon performance or present a grid-disturbing load that earns a worse interconnection deal.

The conventional answer, inherited from the server world, is the multiphase buck VRM. A digital controller drives N interleaved phases. Each phase is a high-side/low-side MOSFET pair (now integrated as a smart power stage, or DrMOS, with current and temperature telemetry built in) feeding an inductor, and all phases sum into a shared output rail. Interleaving multiplies the effective switching frequency at the output and shrinks the ripple, so more phases buy a tighter rail and more current, at the cost of board area, gate-drive losses and controller complexity. A modern GPU core rail can demand 16, 20, or more phases just to source the current without melting any single power stage.

Two design moves dominate. The first is 48V direct conversion versus a two-stage 48V→12V→core path. The industry has moved decisively to higher distribution voltage because, at constant power, quadrupling the voltage cuts distribution current 4x and therefore I²R loss in the board copper 16x. Direct single-stage conversion saves the intermediate-bus-converter losses but stresses the duty cycle. Two-stage is more forgiving but adds a conversion. The same trade has reached the 800 VDC tray. Navitas's 24 kW GaN board, announced on 12 October 2026, takes 800 VDC straight to 12 V and eliminates the 50 V-to-12 V stage. NVIDIA co-developed it for the MGX ecosystem, and it hung on NVIDIA's partner wall at the OCP Global Summit. Its 97% full-load efficiency is a Navitas target. Chapter 4.7 covers the 800 VDC facility side.

The second is the load-line (also called adaptive voltage positioning): you program the regulator so the delivered voltage droops with load current along a defined slope. It sounds backwards to lower the voltage as current rises, but it can reduce the transient excursion by pre-positioning the rail within the negotiated load-line budget. It also lets the silicon run at the lowest voltage that still meets timing, which is pure power savings. The slope is negotiated between the silicon vendor, who owns the timing margin, and the power team, who owns the regulator. Get it wrong and you either burn power or cause timing failures under transients.

Where the final 48V-to-core conversion sits is the central architectural choice. There are three placements, and each has its own current path, thermal path and service boundary.

Board-edge multiphase is the legacy position: the VRM lives on the motherboard, and current crosses the socket and package to reach the die. It is cheap, serviceable and well understood, and increasingly untenable, because resistance from board edge to die dominates the loss budget as core current climbs. Lateral power-on-package puts current-multiplier modules on the package substrate, flanking the die on the north/south or east/west edges, so the final conversion happens millimeters away. Vertical power delivery (VPD) is one placement option: the modules sit directly underneath the processor and feed current straight up into the die by the shortest path. ASE patent US11848296B2 (published December 19, 2023) models one embodiment with 66% lower ESR and 42.8% lower ESL, a simulated path result rather than a measured system efficiency.

VPD is still pre-volume for GPUs. Vicor says its second-generation modules reach a baseline of 3 A/mm² (vendor claim; 5 A/mm² is targeted for 2027). It reports an initial chipset for its lead customer, demonstration systems still being finished, and production systems expected around late Q3 to Q4 2027. In July 2026 Analog Devices completed its $1.5 billion acquisition of Empower Semiconductor, which makes integrated voltage regulators and silicon capacitors. When a vendor pitches VPD, ask for current density under the die, in A/mm² at full load and operating temperature. That number sets the footprint. At 3 A/mm², a 2,000A package needs about 670 mm² of converter. Lateral competitors, which Vicor puts at ~1 A/mm², would need about 2,000 mm². Also ask for efficiency at that current, and whether a failed converter can be swapped without scrapping the module.

A separate, silicon-level choice is backside power delivery (BSPDN): routing the power rails on the back of the wafer, beneath the transistors, instead of competing with signals for the congested metal stack on top. Intel ships it as PowerVia on 18A. Panther Lake client chips have used it since early 2026, and the Xeon 6+ (Clearwater Forest) server CPU has used it since its June 2026 launch. No shipping GPU or AI accelerator with backside power has been announced; TSMC's A16 is the expected first path. TSMC's Super Power Rail comes with A16, and TSMC's April 2026 roadmap pushed A16 volume production to 2027 (from an original 2H-2026 target). Taiwanese press said in August 2026 that production would begin in Q4 2026, but TSMC has not confirmed it. Samsung announced SF2Z with backside power for 2027 in 2024, but the node is absent from its 2026 roadmap, so treat Samsung's timing as unconfirmed.

The payoff is twofold. Intel's 2023 PowerVia test chip showed more than 30% less platform voltage droop and a 6% frequency gain; neither is a converter-efficiency gain. Moving power routing to the backside also frees frontside tracks for signals. Together, lower droop and more routing space improve power integrity and logic density. The catch is thermal: the backside stack and cooling orientation decide which layers sit between the active devices and the cold plate, which complicates the already tight thermal budget covered in Chapter 5.4.

The table compares current paths. Loss in every position grows as the square of the current, so each GPU generation's higher core current makes path resistance and transient control matter more. VPD and BSPDN act on different boundaries: VPD shortens the path through the package, BSPDN the path inside the die. A design can use one, both or neither.

Power integrity comes down to one specification: hold the core rail inside its noise window at every frequency where the load draws current. The load is a digital engine that switches at GHz and gates whole tiles on and off at MHz, so its current demand has spectral content from DC past 100 MHz. The governing rule is the target impedance: Z_target = ΔV_allowed / ΔI_max. For a sub-1V rail with a tight noise budget and a transient of hundreds of amps, that target is well under 1 mΩ out to 100 MHz, and in the microohm range at DC. With the 40 mV allowance and 1,000 A step used in the worked example below, it is 40 µΩ. The PDN's job is to present a flat impedance below that line across the whole band. Any frequency where impedance pokes above the line is a frequency where a load step produces a droop that breaks the noise budget. In a clocked machine, droop means a timing failure, and you answer it by lowering the clock (lost performance) or raising the voltage (lost power).

No single component holds that impedance flat across nine decades of frequency, so the PDN is a hierarchy of decoupling, with each tier owning a frequency band:

• Bulk capacitance (board, µs–ms band): large electrolytic or polymer caps near the VRM that hold the rail through the regulator's own control-loop response time. This is also where the energy for a load step is stored.
• Mid-frequency ceramics (package + board, ~MHz band): MLCCs spread across the package and the board backside, bridging bulk caps and on-die caps. Anti-resonance bites in this band: the parasitic inductance of one tier resonates against the capacitance of the next, producing an impedance peak exactly where you need a valley.
• On-die decoupling (>100 MHz band): MIM and deep-trench capacitors integrated into the silicon, the only thing fast enough for the highest-frequency current steps. As package and board inductance increasingly dominate, the burden shifts on-die. The newest accelerators also add on-die voltage telemetry that reports rail quality in real time so the system can adapt.

The decision is the on-package capacitance budget: how much die area and package real estate you spend on decoupling instead of logic and signal. Spend too little and you fail the target impedance and droop limits. Spend too much and you give up die area, the most expensive real estate on the package, or add package complexity. The budget is co-designed with the load-line slope and the VRM phase count, three knobs that together must meet the impedance target.

A GPU running a synchronous training step does not draw constant current. It draws current that tracks the workload: when thousands of cores fire together at the start of a matrix-multiply tile, current can step hundreds of amps in nanoseconds to microseconds. That rate of change is di/dt, and across the inductance of the PDN it generates a voltage transient: V = L·di/dt. A fast load step pulls the rail down (Vdroop), and the sudden release at the end of a compute burst lets it overshoot up. Either excursion outside the noise window is a fault.

Three lines of defense, in order of speed. On-die capacitance handles the fastest edge, because it is the only charge reservoir close enough to respond in nanoseconds. The load-line pre-positions the rail so the droop lands inside the budget instead of below it. Adaptive clocking / droop detection is the last resort: dedicated on-die circuits sense an impending droop and momentarily stretch the clock to ride it out, trading performance for rail margin within the validated protection behavior. Excessive droop can still fault. The accelerator vendor co-designs all three. The data-center engineer inherits the result as a power profile, a characteristic spike-and-idle waveform whose amplitude, duration, repetition rate and slew must be written into the contract, supplied and tested, because they have consequences three layers up.

Core output = 0.80 V × 2,000 A = 1.6 kW. Path loss = (2,000 A)² × 20 µΩ = 80 W. The 1,000 A step adds 20 mV of resistive drop and 10 pH × (1,000 A/1 µs) = 10 mV of inductive drop, so 30 mV against the 40 mV allowance. Shelf input = 120/0.96 = 125 kW, which leaves 5 kW of conversion heat. The extra 20 kW for 10 ms needs 200 J. The ideal requirement C ≥ 2×200/(50²−46²) F lies between 1.0 and 1.1 F: 1.0 F supplies 192 J and fails, while 1.1 F supplies about 210 J and clears this ideal screen. At 95% efficiency the shelf input is about 126 kW and fails; 96% is the exact input-power threshold. Capacitance does not reduce steady input energy.

The ideal screen leaves out ESR, aging, tolerance, loop stability and protection. Test all five, plus impedance and repeated-pulse duty, dynamically on the rail path and again on the shelf design. Before adding the 80 W rail loss to a separately quoted shelf figure, check where that loss is already counted. Chapter 4.1 does the full loss accounting, and Chapter 4.7 covers the rack waveform and the shelf interface.

On-package power delivery is the last node of a chain this guide reads end to end. Upstream of the package, Chapter 4.7 covers the AC-fed power shelves of shipping racks, the 800 VDC and sidecar architectures planned above ~250 kW, and the busbar. Chapter 4.6 covers the LV distribution, PDUs and rack power that deliver 48V to the board. Chapter 4.5 covers the UPS and energy-storage layer that absorbs the slow envelope of the transient, the facility end of the di/dt spine that starts on the die here. The accelerator whose rail we are feeding is described in Chapter 7.1. The thermal path that now runs through the backside power layer is engineered in Chapter 5.4 against the density wall of Chapter 5.1. The consolidated 2026→2030 subsystem roadmap is in Chapter 16.2.